JPS6415947U - - Google Patents
Info
- Publication number
- JPS6415947U JPS6415947U JP10742687U JP10742687U JPS6415947U JP S6415947 U JPS6415947 U JP S6415947U JP 10742687 U JP10742687 U JP 10742687U JP 10742687 U JP10742687 U JP 10742687U JP S6415947 U JPS6415947 U JP S6415947U
- Authority
- JP
- Japan
- Prior art keywords
- guide groove
- color
- comparator body
- mounting table
- plane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000052 comparative effect Effects 0.000 claims 1
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10742687U JPS6415947U (US20040098680A1-20040520-M00007.png) | 1987-07-13 | 1987-07-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10742687U JPS6415947U (US20040098680A1-20040520-M00007.png) | 1987-07-13 | 1987-07-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6415947U true JPS6415947U (US20040098680A1-20040520-M00007.png) | 1989-01-26 |
Family
ID=31341830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10742687U Pending JPS6415947U (US20040098680A1-20040520-M00007.png) | 1987-07-13 | 1987-07-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6415947U (US20040098680A1-20040520-M00007.png) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6915501B2 (en) | 2001-01-19 | 2005-07-05 | Cadence Design Systems, Inc. | LP method and apparatus for identifying routes |
| US6944841B1 (en) | 2002-01-22 | 2005-09-13 | Cadence Design Systems, Inc. | Method and apparatus for proportionate costing of vias |
| US7003752B2 (en) | 2002-11-18 | 2006-02-21 | Cadence Design Systems, Inc. | Method and apparatus for routing |
| US7013445B1 (en) | 2002-12-31 | 2006-03-14 | Cadence Design Systems, Inc. | Post processor for optimizing manhattan integrated circuits placements into non manhattan placements |
| US7047513B2 (en) | 2002-11-18 | 2006-05-16 | Cadence Design Systems, Inc. | Method and apparatus for searching for a three-dimensional global path |
| US7055120B2 (en) | 2000-12-06 | 2006-05-30 | Cadence Design Systems, Inc. | Method and apparatus for placing circuit modules |
| US7073150B2 (en) | 2000-12-07 | 2006-07-04 | Cadence Design Systems, Inc. | Hierarchical routing method and apparatus that use diagonal routes |
| US7080336B2 (en) | 2000-12-06 | 2006-07-18 | Cadence Design Systems, Inc. | Method and apparatus for computing placement costs |
| US7096449B1 (en) | 2002-01-22 | 2006-08-22 | Cadence Design Systems, Inc. | Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts |
| US7117468B1 (en) | 2002-01-22 | 2006-10-03 | Cadence Design Systems, Inc. | Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts |
| US7155697B2 (en) | 2001-08-23 | 2006-12-26 | Cadence Design Systems, Inc. | Routing method and apparatus |
| US7171635B2 (en) | 2002-11-18 | 2007-01-30 | Cadence Design Systems, Inc. | Method and apparatus for routing |
| US7398498B2 (en) | 2001-08-23 | 2008-07-08 | Cadence Design Systems, Inc. | Method and apparatus for storing routes for groups of related net configurations |
| US7800236B1 (en) * | 2007-02-28 | 2010-09-21 | Integrated Device Technology, Inc. | Semiconductor die and method for forming a semiconductor die having power and ground strips that are oriented diagonally |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5234775A (en) * | 1975-09-12 | 1977-03-16 | Tsuneo Washimi | Colorific meter |
-
1987
- 1987-07-13 JP JP10742687U patent/JPS6415947U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5234775A (en) * | 1975-09-12 | 1977-03-16 | Tsuneo Washimi | Colorific meter |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7080336B2 (en) | 2000-12-06 | 2006-07-18 | Cadence Design Systems, Inc. | Method and apparatus for computing placement costs |
| US7055120B2 (en) | 2000-12-06 | 2006-05-30 | Cadence Design Systems, Inc. | Method and apparatus for placing circuit modules |
| US7073150B2 (en) | 2000-12-07 | 2006-07-04 | Cadence Design Systems, Inc. | Hierarchical routing method and apparatus that use diagonal routes |
| US6915501B2 (en) | 2001-01-19 | 2005-07-05 | Cadence Design Systems, Inc. | LP method and apparatus for identifying routes |
| US7398498B2 (en) | 2001-08-23 | 2008-07-08 | Cadence Design Systems, Inc. | Method and apparatus for storing routes for groups of related net configurations |
| US7155697B2 (en) | 2001-08-23 | 2006-12-26 | Cadence Design Systems, Inc. | Routing method and apparatus |
| US7117468B1 (en) | 2002-01-22 | 2006-10-03 | Cadence Design Systems, Inc. | Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts |
| US7096449B1 (en) | 2002-01-22 | 2006-08-22 | Cadence Design Systems, Inc. | Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts |
| US6944841B1 (en) | 2002-01-22 | 2005-09-13 | Cadence Design Systems, Inc. | Method and apparatus for proportionate costing of vias |
| US7047513B2 (en) | 2002-11-18 | 2006-05-16 | Cadence Design Systems, Inc. | Method and apparatus for searching for a three-dimensional global path |
| US7003752B2 (en) | 2002-11-18 | 2006-02-21 | Cadence Design Systems, Inc. | Method and apparatus for routing |
| US7171635B2 (en) | 2002-11-18 | 2007-01-30 | Cadence Design Systems, Inc. | Method and apparatus for routing |
| US7013445B1 (en) | 2002-12-31 | 2006-03-14 | Cadence Design Systems, Inc. | Post processor for optimizing manhattan integrated circuits placements into non manhattan placements |
| US7800236B1 (en) * | 2007-02-28 | 2010-09-21 | Integrated Device Technology, Inc. | Semiconductor die and method for forming a semiconductor die having power and ground strips that are oriented diagonally |
