JPS6414934A - Semiconductor integrated circuit device and film carrier tape - Google Patents

Semiconductor integrated circuit device and film carrier tape

Info

Publication number
JPS6414934A
JPS6414934A JP16964087A JP16964087A JPS6414934A JP S6414934 A JPS6414934 A JP S6414934A JP 16964087 A JP16964087 A JP 16964087A JP 16964087 A JP16964087 A JP 16964087A JP S6414934 A JPS6414934 A JP S6414934A
Authority
JP
Japan
Prior art keywords
wire
signal transmission
conductor wire
ground conductor
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16964087A
Other languages
Japanese (ja)
Other versions
JP2543894B2 (en
Inventor
Kazuyoshi Saito
Tomoaki Takubo
Toshio Sudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62169640A priority Critical patent/JP2543894B2/en
Priority to EP19880108701 priority patent/EP0293838A3/en
Publication of JPS6414934A publication Critical patent/JPS6414934A/en
Priority to US07/652,371 priority patent/US5162896A/en
Application granted granted Critical
Publication of JP2543894B2 publication Critical patent/JP2543894B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

PURPOSE:To display the high speed performance of a chip in correspondence with the increase in number of input terminals and the implementation of high density, by forming a feed through wiring and a straight line shape without bending in a wire, which is connected to a signal input terminal. CONSTITUTION:In a TAB board, a copper foil is stuck on a flexible long resin film 1, and a signal transmission wire 2, conductor wire 3 and a ground conductor wire 3 and a rear surface ground conductor wire 8 are formed. The ground conductor wire 3 and the rear surface ground conductor wire 8 are connected with a plurality of through hole conductors 5, and a terminating potential is provided. An integrated circuit chip 7 and the signal transmission wire 2 are connected through a protruding electrode 6. The protruding electrode 6 is formed by applying Au plating 62 of a barrier metal layer 61 comprising Ti-Ni-Pd and the like, which is formed on an Al bonding pad 9. The through hole conductors 4 and 5 are formed by Cu plating. Sn plating is applied at the connecting surface with the protruding electrode. The lead-out part of the signal transmission wire 2 is conencted to a terminating potential VTT through a terminating resistor R. The combination of the signal transmission wire 2 and the ground conductors 3 and 8 is adjusted to the specified characteristic impedance. The arranging direction of the signal transmission wire is slightly inclined with respect to the arrangement of an element.
JP62169640A 1987-06-02 1987-07-09 Semiconductor integrated circuit device Expired - Lifetime JP2543894B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP62169640A JP2543894B2 (en) 1987-07-09 1987-07-09 Semiconductor integrated circuit device
EP19880108701 EP0293838A3 (en) 1987-06-02 1988-05-31 Ic package for high-speed semiconductor integrated circuit device
US07/652,371 US5162896A (en) 1987-06-02 1991-02-07 IC package for high-speed semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62169640A JP2543894B2 (en) 1987-07-09 1987-07-09 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS6414934A true JPS6414934A (en) 1989-01-19
JP2543894B2 JP2543894B2 (en) 1996-10-16

Family

ID=15890237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62169640A Expired - Lifetime JP2543894B2 (en) 1987-06-02 1987-07-09 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP2543894B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4991001A (en) * 1988-03-31 1991-02-05 Kabushiki Kaisha Toshiba IC packing device with impedance adjusting insulative layer
DE4117761A1 (en) * 1990-06-01 1991-12-05 Toshiba Kawasaki Kk Semiconductor chip with film carrier - has lead wires between chip terminals and external electrodes applied to surface of film

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831566A (en) * 1981-08-18 1983-02-24 Nec Corp Semiconductor device
JPS6046040A (en) * 1983-08-24 1985-03-12 Nec Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831566A (en) * 1981-08-18 1983-02-24 Nec Corp Semiconductor device
JPS6046040A (en) * 1983-08-24 1985-03-12 Nec Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4991001A (en) * 1988-03-31 1991-02-05 Kabushiki Kaisha Toshiba IC packing device with impedance adjusting insulative layer
DE4117761A1 (en) * 1990-06-01 1991-12-05 Toshiba Kawasaki Kk Semiconductor chip with film carrier - has lead wires between chip terminals and external electrodes applied to surface of film

Also Published As

Publication number Publication date
JP2543894B2 (en) 1996-10-16

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