JPS6412418B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output circuit having an input/output terminal.

In recent years, the number of functions that can be integrated into integrated circuits (hereinafter abbreviated as IC) has increased significantly, and with the increase in functions, the number of input/output signals to the IC has increased. On the other hand, the number of terminals allowed on an IC package cannot be increased to match the increase in functionality due to manufacturing and economic reasons. Therefore, the above-mentioned limitation is solved by employing input/output pins. In addition, as a recent trend, especially in products with functions such as a single-chip CPU, electronically programmable read-only memory (hereinafter referred to as "read-only memory") is installed in the IC chip so that the user can freely change the CPU program.
Products with built-in PROM (abbreviated as PROM) have also been announced. Field-effect transistors (hereinafter referred to as
A write voltage equal to the withstand voltage of the transistor (abbreviated as Tr) is required. When this voltage is applied from the input terminal, the input impedance of the input inverter is extremely high, so an effective input gate protection circuit using high resistance can be used. For protection, a protection circuit with high impedance cannot be used on the output side.

In the conventional circuit, the output terminal of the output inverter is directly connected to the input/output terminal, so when the PROM write voltage is applied to the input/output terminal,
This voltage will be applied to the drain electrode of the output transistor. At this time, the gate electrode of the Tr is
Since the transistor is set to the ground potential to drive it to the off state, the high voltage applied to the drain causes an electric field concentration between the edge of the drain diffusion layer and the gate electrode, which causes an appalance breakdown between the drain diffusion layer and the substrate directly under the gate electrode. There is a risk of permanent destruction of the triggering element.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input/output circuit having an effective voltage protection function on the output side.

The feature of the present invention is to increase the withstand voltage on the output side of the input/output terminal by connecting in series a transistor whose gate voltage is connected to a high voltage such as the power supply voltage between the output terminal of the output inverter and the input/output terminal. output
In addition to protecting the transistor withstand voltage, when the input/output circuit operates as an output, the input/output terminal is driven through the low resistance of the series transistor.

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is an example of an input/output circuit according to the present invention. For convenience of explanation in the figure, the Tr used is an N-channel type, the power supply voltage Vcc used is +5V, the loads TrQ ₂₂ , Q ₂₃ , and Q ₂₄ described below operate in deep mode, and the other transistors are of the N-channel type. It is assumed that the Tr is operating in enhancement mode. Also, logic "0" is approximately ground potential, and logic "1" is approximately ground potential.
When Vcc is defined, the enhancement mode transistor is cut off when the gate voltage is "0" and conductive when the gate voltage is "1". Note that the output point C of the output inverter 32 and the input/output terminal 40 are connected directly (without intervening TrQ ₁ ).
What is connected is a conventional input/output terminal.

A two-input NAND gate 30 which receives I ₁ and I ₂ as inputs is composed of a load TrQ ₂₂ and logic TrQ ₁₂ and Q ₁₃ . _Q22
The drain electrode of is connected to the power supply Vcc, and the gate electrode is connected to the 2-input NAND gate 30 along with the source electrode.
is connected to output point A of The output point A is also connected to the common drains of two TrQ ₁₂ and Q ₁₃ connected in parallel, and the source electrodes of both Trs are also commonly grounded. The gate electrode of Q ₁₂ is connected to input I ₁ , Q ₁₃
The gate electrodes of are respectively connected to the input I ₂ . The 2-input NAND gate 31 is composed of a load TrQ ₂₃ and logic TrQ ₁₄ and Q ₁₅ and has the same configuration as the 2-input NAND gate 30, but the gate electrode of Q ₁₄ is connected to the output point A of the 2-input NAND gate 30. The only difference is that the output is taken out from the connection point B between the source of the output Q ₂₃ and the drains of Q ₁₄ and Q ₁₅ . The output inverter 32 consists of Q ₁₁ and Q ₂₁ which are push-pull connected. The drain electrode of Q ₂₁ is connected to the power supply Vcc,
The gate electrodes are respectively connected to the output point A of the two-input NAND gate 30. The source electrode of Q ₂₁ is commonly connected to the drain electrode of Q ₁₁ and serves as an output point C of the push-pull inverter 32. _Q11
The gate electrode is connected to the output point B of the two-input NAND gate 31, and the source electrode is grounded.

The source electrode of the breakdown voltage protection TrQ _1, which is the main part of the present invention, is connected to the output point C of the push-pull inverter 32, and the drain electrode is connected to the input/output terminal 4.
Connected to 0. Further, the gate electrode is connected to the power supply Vcc.

Input inverter 33 has load TrQ ₂₄ and logic TrQ ₁₆
and a _Q16 gate protection circuit 34. _Q24
The drain electrode of Q16 is connected to the power supply Vcc, and the gate electrode, together with the source electrode, is connected to the drain electrode of _Q16 , and serves as the output point D of the input inverter 33. Further, from the output point D, the input inverter output _O1 when the input/output circuit is operating in the input mode is taken out. The source electrode of Q ₁₆ is grounded, and the gate electrode is connected to the input/output terminal 4 through the gate protection circuit 34.
Driven from 0.

Now, when the input/output circuit operates in the output mode, the I ₂ input is set to "0", and the 2-input NAND gates 30 and 31 send the inverted and non-inverted outputs of the input I ₁ to output points A and B, respectively. Output. That is, when input _I1 is "0", "1" appears at output point A and "0" appears at output point B, and when input I1 is " ₁ ", "0" appears at output point A, and "0" appears at output point B. “1” appears in B. Therefore, when input I ₁ is “0”
The gate electrode of Q ₂₁ is driven to "1" and the gate electrode of Q ₁₁ is driven to "0", so Q ₂₁ is in a conductive state and Q ₁₁ is in a cut-off state, and the output point C is connected to the power supply Vcc.
The voltage Vo obtained by subtracting the threshold voltage VT ₁ ' when the source electrode of Q ₂₁ is not at ground potential but equal to the output voltage is output. On the other hand, when the input I ₁ is "1", Q ₂₁ is cut off and Q ₁₁ is turned on, so that the output point C becomes approximately at the ground potential. Since TrQ ₁ has its gate electrode connected to the power supply Vcc, it is in a completely normal state, and the output voltage at the output point C becomes the output voltage at the input/output terminal 40 as it is. Since the element dimensions of Q ₁ can be freely set, the resistance when Q ₁ is conductive can be sufficiently lowered to a value that does not interfere with the output inverter driving an external load through the input/output terminal 40.

On the other hand, when the input/output circuit operates in the input mode, the I ₂ input is set to "1", so both Q ₁₃ and Q ₁₅ become conductive, so the 2-input NAND gate output A,
Both B become "0" and both Q ₂₁ and Q ₁₁ are also cut off. Therefore, Q ₁ remains conductive, but the impedance seen from the input/output terminal 40 to the output inverter side becomes an extremely high value, so the input/output terminal 40 can be used as an input terminal. Therefore, the voltage applied to the input/output terminal 40 is applied to the gate electrode of the logic TrQ ₁₆ of the input inverter 33 through the input protection circuit 34, so when "0" is applied to the input/output terminal 40, Q ₁₆ is cut off. state and O ₁ is approximately the power supply Vcc (applied voltage) +
5V is output. When the input/output terminal is "1", Q ₁₆ becomes conductive and the O ₁ output becomes approximately at ground potential. That is, the inverted logic output of the input/output terminal 40 appears as the input inverter output _O1 .

Next, in order to clarify the characteristic effects of the present invention, a case will be described in which the input/output circuit is operated in an input mode and a PROM write signal is applied from the input/output terminal 40 as an input signal. In this case, a voltage that is equal to or slightly exceeds the drain breakdown voltage when the gate electrode of the transistor is grounded is selected as the write signal to set the logic "1" level. At this time, the logic “1” is from the input/output terminal 40 to the IC.
It is directly applied to the PROM portion as an internal write signal W. At this time, the voltage is also applied to the gate electrode of _Q16 through the gate protection circuit 34, and the input inverter operates accordingly, but whether or not the input inverter output _O1 is used during PROM writing is irrelevant to the gist of the present invention. A description of the operation of the input inverter 33 in this state will be omitted. “1′” applied to the input/output terminal 40 is conductive.
It is also applied to the output point C of the output inverter 32 through _Q1 , but the voltage Vc at the output _{point C} is Since it is considered to be zero, Vc=Vcc−
VT ₁ ', which is independent of the voltage applied to the input/output terminal 40, and the logic "1'" applied to the input/output terminal 40 will not exceed the output withstand voltage of the output inverter 32. On the other hand, logic “1′” is directly applied to the drain electrode of voltage protection protection TrQ ₁ , but Q ₁
Since the gate electrode of is connected to the power supply Vcc, Q ₁
As described below, the withstand voltage at the drain electrode is increased approximately by the power supply voltage Vcc, and avalanche breakdown does not occur in this region. Figure 2 shows the drain breakdown characteristics of the transistor in the avalanche region. For example, the curve VG ₁ is a curve when the gate voltage is VG ₁ , and it is assumed that VG ₁ <VG ₂ <VG ₃ <VG ₄ <VG ₅ .
Since the drain breakdown voltage of Tr is almost directly proportional to the voltage applied to the gate electrode, the drain breakdown voltage of _Q1 is Vcc
It increases by the voltage.

As described above, according to the present invention, the input/output circuit is sufficiently protected against input voltages exceeding the output voltage of the output inverter, and the output characteristics are not impaired.

Although the above explanation has been made using N-channel transistors, it goes without saying that P-channel transistors may be used, and C-MOS inverters may be used as the input and output inverters.

[Brief explanation of drawings]

FIG. 1 is a circuit connection diagram showing an embodiment of the input/output circuit according to the present invention, and FIG. ₂ is a curve diagram showing drain breakdown characteristics of a transistor in the avalanche region.
...VG ₅ is the gate voltage. Q ₁ ...Protection MOS for enhancement mode
Transistor, Q ₁₁ , Q ₁₂ , Q ₁₃ , Q ₁₄ , Q ₁₅ , Q ₁₆ ,
Q ₂₁ ... Enhancement mode MOS transistor, Q ₂₂ , Q ₂₃ , Q ₂₄ ... Depletion mode
MOS transistor, 30, 31...2 inputs
NAND gate, 32...Output inverter, 33
...Input inverter, 34...Gate protection circuit,
40...Input/output terminal.

Claims (1)

[Claims] 1 An input/output circuit of an integrated circuit including a PROM, including an input inverter, an output inverter, an input/output terminal, and an input gate protection inserted between the input section of the input inverter and the input/output terminal. The circuit is inserted between the output part of the output inverter and the input/output terminal, a source electrode is connected to the output end of the output inverter, a drain electrode is connected to the input/output terminal, and a gate electrode is connected to the input/output terminal. The device is characterized by comprising a field effect transistor connected to a power source, and means for setting the output impedance of the output inverter to a high impedance state when a high voltage for writing to the PROM is applied to the input/output terminal. Input/output circuit.