JPS6399560A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6399560A JPS6399560A JP61245824A JP24582486A JPS6399560A JP S6399560 A JPS6399560 A JP S6399560A JP 61245824 A JP61245824 A JP 61245824A JP 24582486 A JP24582486 A JP 24582486A JP S6399560 A JPS6399560 A JP S6399560A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- wiring
- board
- chip
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 239000000758 substrate Substances 0.000 claims description 21
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000006870 function Effects 0.000 description 18
- 230000000694 effects Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 239000002131 composite material Substances 0.000 description 2
- 229910020220 Pb—Sn Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ひとつのパッケージ内に多数個の半導体チッ
プを実装してなる、いわゆる三次元実装マルチチップパ
ッケージ技術による半導体装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvement of a semiconductor device using so-called three-dimensional mounting multi-chip packaging technology, in which a large number of semiconductor chips are mounted in one package.
従来からこの種の半導体装置として、複数個の半導体チ
ップ（ＬＳＩチップ）を、複数枚の配線基板にそれぞれ
平面実装するとともに、これら配線基板を順次積層方向
に並設した状態で別の配線基板上に設け、さらにこれら
をひとつのパッケージ内に実装してなる構成を有するも
のが知られている。このような従来の三次元実装マルチ
チップパッケージを第３図（ａ） 、 （ｂ） 、 （
ｃ）を用いて簡単に説明すると、図中１はＰＮ接合から
なる能動素子およびその接続用配線を有し能動、受動機
能を備えてなるＳｔ等による多数個の半導体チップで、
これら半導体チップ１はそれぞれがたとえば大容量メモ
リ、マイクロプロセッサの大規模論理回路等の一定規模
の機能を有し、かつこれら多数個の半導体チップ１全部
でこの半導体装置全体の機能が構成される。２はこれら
多数個の半導体チップ１が複数個づつ配置固定されその
機能を相互に接続する複数枚の第１配線基板、３はこれ
らの第１配線基板が立設状態で並設されることでその機
能を相互に接続する第２配線基板で、これら第１および
第２配線基板２，３は前記多数個の半導体チップ１と共
に絶縁基板４上に載置されることでパッケージ化されて
いる。ここで、図中５ａは前記各半導体チップｌ上に形
成されこれを＄１配線基板２偏に電気的、機械的に接続
するためのＰｂ・Ｓｎ合金による電極（以下バンプとい
う）、５ｂはｌ’Ｇ１配線基板２を第２配線基板側に電
気的および機械的に接続するＰｂ＊Ｓｎ合今による電極
（バンプ）で、また６は第２配線基板３と絶縁基板４を
電気的に接続するワイヤ、７はこの半導体装置の機能を
外部に取出すための外部接続用電極（外部ビン）である
。Conventionally, as this type of semiconductor device, a plurality of semiconductor chips (LSI chips) are planarly mounted on a plurality of wiring boards, and these wiring boards are sequentially arranged side by side in the stacking direction and mounted on another wiring board. It is known to have a configuration in which these devices are provided in a single package. Such conventional three-dimensional mounting multi-chip packages are shown in Fig. 3 (a), (b), (
To briefly explain using c), 1 in the figure is a large number of semiconductor chips made of St, etc., which have active elements made of PN junctions and wiring for connecting them, and are equipped with active and passive functions.
Each of these semiconductor chips 1 has a certain function, such as a large-capacity memory or a large-scale logic circuit of a microprocessor, and the functions of the entire semiconductor device are constituted by all of these semiconductor chips 1. 2 is a plurality of first wiring boards on which a plurality of semiconductor chips 1 are arranged and fixed and their functions are connected to each other; 3, these first wiring boards are arranged side by side in an upright state; The first and second wiring boards 2 and 3 are packaged together with the plurality of semiconductor chips 1 by being placed on an insulating substrate 4, which is a second wiring board that interconnects their functions. Here, in the figure, 5a is an electrode (hereinafter referred to as a bump) made of a Pb-Sn alloy formed on each semiconductor chip l to electrically and mechanically connect it to the $1 wiring board 2, and 5b is l. 'G1 is an electrode (bump) made of a Pb*Sn composite that electrically and mechanically connects the wiring board 2 to the second wiring board side, and 6 electrically connects the second wiring board 3 and the insulating board 4. Wire 7 is an external connection electrode (external via) for extracting the function of this semiconductor device to the outside.
このような構成による半導体装置において、半導体チッ
プ１の主面に形成したＰＮ接合はＡＩ等による配線（図
示せず）で相互に接続され、ＰＮ接合による電気的機能
はその主面と同一平面上の任意の位置から取出される構
成とされている。したがって、この半導体チップ１の主
面を第１配線基板２の主面（基板面）と平行して対向配
置すれば、その間隙に配置されたバンプ５ａをリフロー
ポンディングすることで、この半導体チップｌの機能と
第１配線基板２の配線を電気的に接続し、同時にこの半
導体チップ１を第１配線基板２上に固定することができ
るものである。そして、この第１配線基板２の主面には
半導体チップｌを相互に接続する配線、相互接続配線（
図示せず）が予め形成されているので、上述したように
して実装された各半導体チップｌの機能は互いに接続、
複合される。その結果、この第１配線基板２は、このよ
うにして搭載された複数個の半導体チップｌの個数分だ
けの機能（サブシステム）を構成することになる。In a semiconductor device having such a configuration, the PN junctions formed on the main surface of the semiconductor chip 1 are connected to each other by wiring (not shown) using AI or the like, and the electrical functions of the PN junctions are performed on the same plane as the main surface. The structure is such that it can be taken out from any location. Therefore, if the main surface of the semiconductor chip 1 is placed parallel to and facing the main surface (substrate surface) of the first wiring board 2, the bumps 5a placed in the gap can be reflow bonded to form the semiconductor chip. 1 and the wiring of the first wiring board 2, and at the same time can fix the semiconductor chip 1 onto the first wiring board 2. The main surface of the first wiring board 2 includes wiring for interconnecting the semiconductor chips l, and interconnection wiring (
(not shown) is formed in advance, the functions of each semiconductor chip l mounted as described above are connected to each other,
Compounded. As a result, this first wiring board 2 constitutes as many functions (subsystems) as the number of semiconductor chips l mounted in this manner.
一方、このような複数個の半導体チップ１を搭載した第
１配線基板２は、第２配線基板３の主面（基板面）と接
触する外周部の一辺に配置した電極５ｂをリフローポン
ディングすることで、第２配線基板３の主面上に垂直な
立設状態で配置され、これによりこの第１配線基板２を
第２配線基板３−トに電気的に接続し、またこれと同時
に機械的にも固定している６そして、この第２配線基板
３の主面には、第１配線基板２を相互に接続する配線、
相互接続配線（図示せず）が予め形成されているため、
これに搭載した前記第１配線基板２上の個々の機能（サ
ブシステム）は互いに接続、複合されることとなる。し
たがって、この第２配。On the other hand, in the first wiring board 2 on which a plurality of semiconductor chips 1 are mounted, the electrodes 5b arranged on one side of the outer periphery in contact with the main surface (substrate surface) of the second wiring board 3 are reflow bonded. This allows the first wiring board 2 to be placed vertically on the main surface of the second wiring board 3, thereby electrically connecting the first wiring board 2 to the second wiring board 3, and at the same time mechanically connecting the first wiring board 2 to the second wiring board 3. Also, on the main surface of this second wiring board 3, there are wires that connect the first wiring board 2 to each other,
Because interconnect wiring (not shown) is pre-formed,
The individual functions (subsystems) on the first wiring board 2 mounted thereon are connected and combined with each other. Therefore, this second allocation.
線基板３上に、前記第１配線基板２のサブシステムの全
部すなわちこの半導体装置に収納した多数個の半導体チ
ップｌのすべての個々の機能を搭載して複合してなる構
成とし得るものである。All of the subsystems of the first wiring board 2, that is, all the individual functions of the multiple semiconductor chips l housed in this semiconductor device, can be mounted on the wiring board 3 to form a composite structure. .
また、この第２配線基板３を前記絶縁基板４に接着剤（
図示せず）で機械的に固定した後、第２配線基板３上に
形成した機能取出し用電極（図示せず）と絶縁基板４上
に形成した配線（図示せず）とを、Ａｕ等によるワイヤ
６で電気的に接続することによって、この第２配線基板
３の全機能が絶縁基板４側に継がる。そして、この絶縁
基板４上の配線は、この半導体装置の機能を外部に取出
す外部接続用電極（外部ビン）７に接続されているため
、結局半導体チップｌ、バンプ５ａ、第１配線基板２、
電極５ｂ、第２配線基板３、ワイヤ６、外部ビン７を通
じて半導体装置の全機能が完成し、外部に伝達すること
が可能となるものである。Further, this second wiring board 3 is attached to the insulating board 4 using an adhesive (
After mechanically fixing the function extraction electrode (not shown) formed on the second wiring board 3 and the wiring (not shown) formed on the insulating substrate 4 using Au or the like, By electrically connecting with the wire 6, all functions of the second wiring board 3 are transferred to the insulating board 4 side. Since the wiring on this insulating substrate 4 is connected to an external connection electrode (external bin) 7 that extracts the functions of this semiconductor device to the outside, the semiconductor chip l, the bumps 5a, the first wiring board 2,
All functions of the semiconductor device are completed through the electrode 5b, the second wiring board 3, the wire 6, and the external via 7, and can be transmitted to the outside.
なお、前記絶縁基板４上には、半導体チップ１、第１配
線基板２、第２配線基板３、ワイヤ６等を物理的、化学
的に保護する蓋体（図示せず）が被冠して取付けられる
ので、通常の取扱いではこの機能が損傷されることはな
く、マルチチップパッケージ化された半導体装置として
動作されるものであった。Note that a lid (not shown) is provided on the insulating substrate 4 to physically and chemically protect the semiconductor chip 1, the first wiring board 2, the second wiring board 3, the wires 6, etc. Because the device was attached, its function would not be damaged by normal handling, and the device could be operated as a multi-chip packaged semiconductor device.
ところで、上述した従来装置によれば、半導体チップｌ
を搭載した第１配線基板２を、第２配線基板３の基板面
に接触する第１配線基板２外周の一辺に設けたＰｂｌｌ
Ｓｎ合金による電極５ｂによって、この第２配線基板３
の基板面上に立設状態で片持ち式に固定するので、これ
ら第１配線基板２と第２配線基板３との機械的接続強度
は、その電極５ｂの設けられていない側の面、すなわち
裏面側から加えられる力に弱い性質をもっていた。これ
は片持ち式による固定構造上から生じる必然的な特徴で
、振動等の両振り荷重に弱く、信頼度が低いという欠点
に繋がるものであった。By the way, according to the conventional device described above, the semiconductor chip l
The first wiring board 2 mounted with the Pbll is provided on one side of the outer periphery of the first wiring board 2 in contact with the board surface of the second wiring board 3.
This second wiring board 3 is made of an Sn alloy electrode 5b.
Since the first wiring board 2 and the second wiring board 3 are fixed in a cantilever manner in an upright state on the board surface, the mechanical connection strength between the first wiring board 2 and the second wiring board 3 is limited to the surface on which the electrodes 5b are not provided, that is, It had the property of being weak against force applied from the back side. This is an inevitable feature due to the cantilevered fixed structure, which leads to the disadvantage that it is susceptible to swinging loads such as vibration and has low reliability.
そして、その一方において、このような機械的強度を大
きくするために電極５ｂの断面積を大きくすると、第１
配線基板２と第２配線基板３との接線」二に並ぶ電極５
ｂ同士が短絡するので、配置できる電極数を減少させな
ければならず、これにより第１配線基板２のサブシステ
ムの信号端子数を減少させ、結果としてサブシステムの
規模を縮少しなければならないものであった。また、こ
れとは逆に大規模システムを三次元実装マルチチップパ
ッケージに組立てようとすると、電極数が増加し、電極
５ｂの断面積が減少して再配線基板２．３間の機械的接
続強度が弱くなり、信頼度が低下するという問題を生じ
てしまうものであった。On the other hand, if the cross-sectional area of the electrode 5b is increased in order to increase the mechanical strength, the first
Electrodes 5 lined up on the tangent between the wiring board 2 and the second wiring board 3
Since the terminals b are short-circuited, the number of electrodes that can be arranged must be reduced, thereby reducing the number of signal terminals of the subsystem on the first wiring board 2, and as a result, the scale of the subsystem must be reduced. Met. On the other hand, when attempting to assemble a large-scale system into a three-dimensional multi-chip package, the number of electrodes increases, the cross-sectional area of the electrodes 5b decreases, and the mechanical connection between the rewiring boards 2 and 3 increases. This resulted in problems such as a decrease in reliability and a decrease in reliability.
すなわち、このような従来装置では、第１配線基板２と
第２配線基板３との機械的強度を大きくしようとすると
、その半導体装置の信頼度が低下したり、第１配線基板
２のサブシステムの規模を縮少させなければならないと
いう問題をもつもので、これらの問題点を一掃し得る何
らかの対策を講じることが望まれている。That is, in such a conventional device, if an attempt is made to increase the mechanical strength between the first wiring board 2 and the second wiring board 3, the reliability of the semiconductor device may decrease or the subsystem of the first wiring board 2 may deteriorate. There is a problem in that the scale of the problem must be reduced, and it is desired that some kind of measures be taken to eliminate these problems.
本発明は上述した事情に鑑みてなされたもので、その装
置の信頼度を低下させずに、しかも大規模システムを構
成することが可能となる半導体装置を得ることを目的と
している。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to obtain a semiconductor device that can be configured into a large-scale system without reducing the reliability of the device.
本発明に係る半導体装置は、複数個の半導体チップを基
板面上に実装してなる複数枚の第１配線基板と、これら
を立設状態で積層方向に並設する基板面を有し第１配線
基板と直交して配置される第２配線基板と、この第２配
線基板が搭載して固定され外部接続用電極を有する絶縁
基板を備え、第１配線基板上に実装される半導体チップ
のうちのひとつの側面を、この第１配線基板が立設され
ている第２配線基板の基板面上に接触させるように構成
したものである。A semiconductor device according to the present invention includes a plurality of first wiring boards each having a plurality of semiconductor chips mounted on the board surface, and a board surface on which these are arranged in an upright state in parallel in a stacking direction. A semiconductor chip mounted on the first wiring board, comprising a second wiring board disposed orthogonally to the wiring board, and an insulating board on which the second wiring board is mounted and fixed and has external connection electrodes. One side surface of the first wiring board is configured to be brought into contact with the substrate surface of the second wiring board on which the first wiring board is erected.
本発明によれば、第２配線基板上に側面が接触する半導
体チップによって、この半導体チップが実装されている
第１配線基板の片持ち式の固定構造を補強することによ
り、これら再配線基板間の機械的接続強度を大きくし得
るものである。According to the present invention, by reinforcing the cantilever type fixing structure of the first wiring board on which this semiconductor chip is mounted by the semiconductor chip whose side surface is in contact with the second wiring board, the connection between these rewiring boards is achieved. The mechanical connection strength can be increased.
以下、本発明を図面に示した実施例を用いて詳細に説明
する。Hereinafter, the present invention will be explained in detail using embodiments shown in the drawings.
第１図（ａ） 、 （ｂ） 、 （ｃ） 、 （ｄ）は
本発明に係る半導体装置の一実施例を示すものであり、
これらの図において前述した第３図（ａ） 、 （ｂ）
、 （ｃ）と同一または相当する部分には同一番号を
付してその説明は省略する。FIGS. 1(a), (b), (c), and (d) show an embodiment of a semiconductor device according to the present invention,
In these figures, the above-mentioned figures 3(a) and (b)
, Parts that are the same as or correspond to (c) are given the same numbers and their explanations are omitted.
さて、本発明によれば、複数個の半導体チップ１と、こ
れら複数個の半導体チップ１を基板面上に実装してなる
複数枚の第１配線基板２と、これら第１配線基板２を立
設状態で積層方向に並設する基板面を有し第１配線基板
２と直交して配置される第２配線基板３と、この第２配
線基板３が搭載して固定され外部接続用電極７を有する
絶縁基板４とを備え、第１配線基板２」−に実装される
半導体チップ１のうちのひとつの側面１ａを、この第１
配線基板２が立設されている第２配線基板３の基板面一
ヒに接触させるように構成したところに特徴を有してい
る。Now, according to the present invention, a plurality of semiconductor chips 1, a plurality of first wiring boards 2 each having a plurality of semiconductor chips 1 mounted on a substrate surface, and a plurality of first wiring boards 2 are arranged to stand up. A second wiring board 3 having board surfaces arranged in parallel in the stacking direction in the installed state and disposed perpendicular to the first wiring board 2; and an external connection electrode 7 on which the second wiring board 3 is mounted and fixed. The side surface 1a of one of the semiconductor chips 1 mounted on the first wiring board 2'' is
The wiring board 2 is characterized in that it is configured to be brought into contact with the substrate surface of the second wiring board 3 on which the wiring board 2 is standing.
すなわち、上述した第１配線基板２に対しバンブ５ａで
半導体チップｌを実装するにあたって、少なくともひと
つを、その側面１ａが第２配線基板３の基板面上に接す
るような位置に実装する。That is, when mounting the semiconductor chips 1 on the first wiring board 2 described above using the bumps 5a, at least one is mounted at a position such that its side surface 1a is in contact with the substrate surface of the second wiring board 3.
そして、このような第１配線基板２の一側面を第２配線
基板３上に接触させて固定する際に、−上述した半導体
チップ１の側面１ａをも第２配線基板３上に接触させる
とよいものである。そして、この状態で前記第１配線基
板２の側面を電極５ｂで第２配線基板３偏に固定すれば
、第１配線基板２側面と半導体チップ側面１８間の中央
部に電極５ｂを介在させてなる固定状態が得られるもの
である。なお、この第２配線基板３はその基板面を Ｏ
電気的に絶縁しているので、半導体チップ側面１ａ１！
−第２配線基板３とは電気的に独立しており、その機能
が損なわれることはない。When one side surface of the first wiring board 2 is brought into contact with and fixed on the second wiring board 3, - the side surface 1a of the semiconductor chip 1 mentioned above is also brought into contact with the second wiring board 3. It's good. In this state, if the side surface of the first wiring board 2 is fixed to the second wiring board 3 with the electrode 5b, the electrode 5b is interposed in the center between the side surface of the first wiring board 2 and the semiconductor chip side surface 18. This results in a fixed state. Note that since the second wiring board 3 electrically insulates the board surface, the semiconductor chip side surface 1a1!
- It is electrically independent from the second wiring board 3, and its function is not impaired.
そして、このような構成において、第１配線基板２の表
面から力を加えると、力点は中央の電極５ｂ、支点は第
１配線基板２の裏面と第２配線基板３の主面と接触する
接線となり、また逆に第１配線基板２の裏面から力を加
えると、力点は同じく中央の電極５ｂ、支点は半導体チ
ップ１の裏面と第２配線基板３の基板面上に接触する接
線となる。このときの破断強度は、中央の電極５ｂの材
料強度に依存するが、半導体チップ１と第１配線基板２
の厚みは略々同じであることから、これら両方向からの
力に対して略々同程度の機械的接続強度をもつことにな
る。つまり、このような本発明による構造によれば、振
動等の両振り荷重に強くなるように作用する。In such a configuration, when force is applied from the surface of the first wiring board 2, the point of force is the central electrode 5b, and the fulcrum is the tangent line that contacts the back surface of the first wiring board 2 and the main surface of the second wiring board 3. And conversely, when force is applied from the back surface of the first wiring board 2, the point of force is also the center electrode 5b, and the fulcrum is the tangent that contacts the back surface of the semiconductor chip 1 and the board surface of the second wiring board 3. The breaking strength at this time depends on the material strength of the central electrode 5b.
Since the thicknesses of the two are approximately the same, they have approximately the same mechanical connection strength against forces from both directions. In other words, the structure according to the present invention acts so as to be strong against swinging loads such as vibrations.
したがって、本発明による構造では、片持ち式のように
一方向の力に弱いといった問題はなくなり、従来のよう
に機械的強度を大きくするために、電極５ａの断面積を
大きくするといった対策は不要で、しかも＄１配線基板
２のサブシステムの信号端子数を増加させることが可能
となり、これにより大規模システムを三次元実装マルチ
チップパッケージに組立てることが可能となる。Therefore, the structure according to the present invention does not have the problem of being weak against force in one direction as in the case of a cantilever type, and there is no need to take measures such as increasing the cross-sectional area of the electrode 5a in order to increase mechanical strength as in the past. Moreover, it becomes possible to increase the number of signal terminals of the subsystem of the $1 wiring board 2, and thereby it becomes possible to assemble a large-scale system into a three-dimensionally mounted multi-chip package.
第２図は本発明の別の実施例を示すものであって、この
実施例では、第２配線基板３上に接する半導体チップ１
を複数個用いた場合であり、その作用効果は容易に理解
されよう。FIG. 2 shows another embodiment of the present invention, in which a semiconductor chip 1 in contact with a second wiring board 3 is shown.
This is the case when a plurality of these are used, and their effects can be easily understood.
なお、本発明は上述した実施例構造に限定されず、各部
の形状、構造等を、適宜変形、変更することは自由であ
る。たとえば上述した実施例では、絶縁基板４上に一枚
の第２配線基板３を搭載した場合を説明したが、この絶
縁基板４上に複数枚の第２配線基板３を搭載してもよい
ことは勿論である。Note that the present invention is not limited to the structure of the embodiment described above, and the shape, structure, etc. of each part may be modified and changed as appropriate. For example, in the above-mentioned embodiment, a case was explained in which one second wiring board 3 was mounted on the insulating substrate 4, but a plurality of second wiring boards 3 may be mounted on the insulating board 4. Of course.
さらに、上述した実施例では、半導体チップ１を、論理
回路ＬＳＩチップとして説明したが、メモリ、センサ等
の他の機能をもつものであってもよく、またＬＳＩに限
らず、ＭＳｌ、ＳＳＩであってもよいことも容易に理解
されよう。さらに、半導体チップ１に能動素子がなく、
配線、抵抗、容量等の受動素子だけが形成されているも
のでもよく、また半導体チップ１、第１配線基板２、第
２配線基板３以外にコイル、コンデンサ等の受動素子を
搭載するようにしてもよい。Furthermore, in the above-described embodiment, the semiconductor chip 1 was explained as a logic circuit LSI chip, but it may also have other functions such as a memory or a sensor. It is easy to understand that it may be possible. Furthermore, the semiconductor chip 1 has no active elements,
It may be possible to form only passive elements such as wiring, resistance, capacitance, etc., or it may be possible to mount passive elements such as coils and capacitors in addition to the semiconductor chip 1, the first wiring board 2, and the second wiring board 3. Good too.
以上説明したように、本発明に係る半導体装置によれば
、複数個の半導体チップと、これらを基板面上に実装し
てなる複数枚の第１配線基板と、これら第１配線基板を
立設状態で積層方向に並設する基板面を有し第１配線基
板と直交して配置される第２配線基板と、この第２配線
基板が搭載して固定され外部接続用電極を有する絶縁基
板を備え、第１配線基板上に実装される半導体チップの
うちの少なくともひとつの側面を、この第１配線基板が
立設されている第２配線基板の基板面上に接触させるよ
うにしたので、簡単かつ安価な構成にもかかわらず、第
１配線基板と第２配線基板との機械的接続強度を従来に
比べ大きくすることが可能で、これにより振動等の両振
り荷重に強くなり、信頼度を向上させ得るという種々優
れた効果がある。そして、このような本発明によれば、
片持ち式のように一方向への力に弱くないので、機械的
強度を大きくしようとして電極の断面積を大きくすると
いった構成は不要で、第１配線基板のサブシステムの信
号端子数を増加させることも可能で、これにより大規模
システムを三次元実装マルチチップパッケージに組立て
ることができる等、その効果は大きい。As explained above, according to the semiconductor device according to the present invention, there are a plurality of semiconductor chips, a plurality of first wiring boards formed by mounting these on a substrate surface, and a plurality of first wiring boards that are installed in an upright manner. a second wiring board having substrate surfaces arranged in parallel in the stacking direction and disposed perpendicular to the first wiring board; and an insulating board on which the second wiring board is mounted and fixed and having external connection electrodes. In this structure, at least one side surface of the semiconductor chip mounted on the first wiring board is brought into contact with the surface of the second wiring board on which the first wiring board is erected. And despite its inexpensive configuration, it is possible to increase the mechanical connection strength between the first wiring board and the second wiring board compared to the conventional one, which makes it resistant to vibrations and other swing loads, improving reliability. There are various excellent effects that can be improved. According to the present invention,
Since it is not susceptible to force in one direction like a cantilever type, there is no need to increase the cross-sectional area of the electrode in order to increase mechanical strength, and the number of signal terminals of the subsystem on the first wiring board can be increased. This has great effects, such as the ability to assemble large-scale systems into three-dimensionally mounted multi-chip packages.
第１図（ａ）、（ｂ）、（Ｃ）、（ｄ）は本発明に係る
半導体装置の一実施例を示す概略斜視図、正面図、側面
図およびそのＡ部詳細図、第２図は本発明の別の実施例
を示す正面図、第３図（ａ） 、 （ｂ） 、 （ｃ）
は従来例を示す概略斜視図、側面図およびそのＢ部詳細
図である。
１・・・・半導体チー、ブ、ｌａ・・・・側面、２・・
・・第１配線基板、３・・・・第２配線基板、４・・・
・絶縁基板、５ａ・・・・バンブ、５ｂ・・・・電極（
バンブ）、６・・・・ワイヤ、７・・・・外部接続用電
極。
’５−1(a), (b), (C), and (d) are a schematic perspective view, a front view, a side view, and a detailed view of part A of the semiconductor device according to an embodiment of the present invention; FIG. 3(a), (b), (c) are front views showing another embodiment of the present invention.
These are a schematic perspective view, a side view, and a detailed view of part B thereof showing a conventional example. 1...Semiconductor chip, b, la...side, 2...
...First wiring board, 3...Second wiring board, 4...
・Insulating substrate, 5a... bump, 5b... electrode (
), 6...Wire, 7...External connection electrode. '5-
Claims (1)
プを基板面上に実装してなる複数枚の第１配線基板と、
これら第１配線基板を立設状態で積層方向に並設する基
板面を有し前記第１配線基板と直交して配置される少な
くとも一枚の第２配線基板と、この第２配線基板が搭載
して固定され外部接続用電極を有する絶縁基板とを備え
、前記第１配線基板上に実装される半導体チップのうち
の少なくともひとつの側面を、この第１配線基板が立設
されている第２配線基板の基板面上に接触させたことを
特徴とする半導体装置。a plurality of semiconductor chips; a plurality of first wiring boards formed by mounting the plurality of semiconductor chips on a substrate surface;
At least one second wiring board having board surfaces arranged in parallel in the stacking direction with these first wiring boards in an upright state and disposed orthogonally to the first wiring boards, and this second wiring board mounted and an insulating substrate fixed to the substrate and having external connection electrodes, the side surface of at least one of the semiconductor chips mounted on the first wiring substrate is fixed to the second wiring substrate on which the first wiring substrate is erected. A semiconductor device characterized in that it is brought into contact with a substrate surface of a wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61245824A JPS6399560A (en) | 1986-10-15 | 1986-10-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61245824A JPS6399560A (en) | 1986-10-15 | 1986-10-15 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6399560A true JPS6399560A (en) | 1988-04-30 |
| JPH0531827B2 JPH0531827B2 (en) | 1993-05-13 |
Family
ID=17139400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61245824A Granted JPS6399560A (en) | 1986-10-15 | 1986-10-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6399560A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7282789B2 (en) * | 1998-03-31 | 2007-10-16 | Micron Technology, Inc. | Back-to-back semiconductor device assemblies |
-
1986
- 1986-10-15 JP JP61245824A patent/JPS6399560A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7282789B2 (en) * | 1998-03-31 | 2007-10-16 | Micron Technology, Inc. | Back-to-back semiconductor device assemblies |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0531827B2 (en) | 1993-05-13 |
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