JPS6395638A - Lsi chip packaging structure - Google Patents

Lsi chip packaging structure

Info

Publication number
JPS6395638A
JPS6395638A JP24131486A JP24131486A JPS6395638A JP S6395638 A JPS6395638 A JP S6395638A JP 24131486 A JP24131486 A JP 24131486A JP 24131486 A JP24131486 A JP 24131486A JP S6395638 A JPS6395638 A JP S6395638A
Authority
JP
Japan
Prior art keywords
chip
carrier substrate
formation
groups
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24131486A
Other versions
JPH0738401B2 (en
Inventor
Hiroshi Honjo
Fumio Nakano
Tasao Soga
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP24131486A priority Critical patent/JPH0738401B2/en
Publication of JPS6395638A publication Critical patent/JPS6395638A/en
Publication of JPH0738401B2 publication Critical patent/JPH0738401B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Lifetime legal-status Critical

Links

Abstract

PURPOSE: To cope adaptively with any alteration of a chip size by arranging connection pad groups that are formed on a carrier substrate so that they may correspond to solder bump groups that are formed on a chip, and composing the pad group of repeated units of divisible connection pad groups.
CONSTITUTION: Connection pads 6 of a carrier substrate 2 carrying an LSI chip 1 correspond to the arrangement of solder bumps 4 on the chip so as to perform a flip chip bonding. Even on the other plane of the carrier substrate 2, the connection pads 7 are prepared at respective corresponding positions and are used for connecting the chip with the solder bumps and then, the pads at both faces are electrically connected with through hole conductors 5. On the occasion of manufacturing the carrier substrate, such a formation of connection pad groups permits the carrier substrate to use commonly a photolithography pattern and also copes with scaling up of a chip size easily. Further, it is possible for this device to have the standardized pad formation, through hole formation, through hole conductor formation and so on and improve the productivity of the carrier substrate as well as that of an LST chip packaging structure in the long run.
COPYRIGHT: (C)1988,JPO&Japio
JP24131486A 1986-10-13 1986-10-13 Lsi chip mounting structure Expired - Lifetime JPH0738401B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24131486A JPH0738401B2 (en) 1986-10-13 1986-10-13 Lsi chip mounting structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP24131486A JPH0738401B2 (en) 1986-10-13 1986-10-13 Lsi chip mounting structure
KR870010825A KR880005683A (en) 1986-10-13 1987-09-29 Lsi chip mounting (實 裝) structure

Publications (2)

Publication Number Publication Date
JPS6395638A true JPS6395638A (en) 1988-04-26
JPH0738401B2 JPH0738401B2 (en) 1995-04-26

Family

ID=17072448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24131486A Expired - Lifetime JPH0738401B2 (en) 1986-10-13 1986-10-13 Lsi chip mounting structure

Country Status (2)

Country Link
JP (1) JPH0738401B2 (en)
KR (1) KR880005683A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0294532A (en) * 1988-09-30 1990-04-05 Hitachi Ltd Semiconductor package and computer using same
JPH0476219U (en) * 1990-11-15 1992-07-03
US5166773A (en) * 1989-07-03 1992-11-24 General Electric Company Hermetic package and packaged semiconductor chip having closely spaced leads extending through the package lid
JPH06224259A (en) * 1992-11-18 1994-08-12 Matsushita Electron Corp Semiconductor device and manufacture thereof
US5705858A (en) * 1993-04-14 1998-01-06 Nec Corporation Packaging structure for a hermetically sealed flip chip semiconductor device
US6037665A (en) * 1997-03-03 2000-03-14 Nec Corporation Mounting assembly of integrated circuit device and method for production thereof
JP2002523900A (en) * 1998-08-25 2002-07-30 コミツサリア タ レネルジー アトミーク Method of manufacturing an integrated electronic circuit comprising at least one power electronic components of the electronic circuit and the substrate
JP2003508898A (en) * 1999-08-26 2003-03-04 ハネウェル・インコーポレーテッド Internal connection method between micro beam assembly and the integrated circuit and the substrate
EP1359617A1 (en) * 2002-04-29 2003-11-05 Valtronic S.A. Process of fabrication of electronic modules

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0294532A (en) * 1988-09-30 1990-04-05 Hitachi Ltd Semiconductor package and computer using same
US5166773A (en) * 1989-07-03 1992-11-24 General Electric Company Hermetic package and packaged semiconductor chip having closely spaced leads extending through the package lid
JPH0476219U (en) * 1990-11-15 1992-07-03
JPH06224259A (en) * 1992-11-18 1994-08-12 Matsushita Electron Corp Semiconductor device and manufacture thereof
US5705858A (en) * 1993-04-14 1998-01-06 Nec Corporation Packaging structure for a hermetically sealed flip chip semiconductor device
US6037665A (en) * 1997-03-03 2000-03-14 Nec Corporation Mounting assembly of integrated circuit device and method for production thereof
US6297141B1 (en) 1997-03-03 2001-10-02 Nec Corporation Mounting assembly of integrated circuit device and method for production thereof
JP2002523900A (en) * 1998-08-25 2002-07-30 コミツサリア タ レネルジー アトミーク Method of manufacturing an integrated electronic circuit comprising at least one power electronic components of the electronic circuit and the substrate
JP2003508898A (en) * 1999-08-26 2003-03-04 ハネウェル・インコーポレーテッド Internal connection method between micro beam assembly and the integrated circuit and the substrate
EP1359617A1 (en) * 2002-04-29 2003-11-05 Valtronic S.A. Process of fabrication of electronic modules
WO2003094229A1 (en) * 2002-04-29 2003-11-13 Valtronic S.A. Method of producing electronic units

Also Published As

Publication number Publication date
JPH0738401B2 (en) 1995-04-26
KR880005683A (en) 1988-06-30

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