JPS6390996U - - Google Patents

Info

Publication number
JPS6390996U
JPS6390996U JP1986184528U JP18452886U JPS6390996U JP S6390996 U JPS6390996 U JP S6390996U JP 1986184528 U JP1986184528 U JP 1986184528U JP 18452886 U JP18452886 U JP 18452886U JP S6390996 U JPS6390996 U JP S6390996U
Authority
JP
Japan
Prior art keywords
trigger signal
power source
rectifying
trigger
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986184528U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986184528U priority Critical patent/JPS6390996U/ja
Publication of JPS6390996U publication Critical patent/JPS6390996U/ja
Pending legal-status Critical Current

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  • Control Of Ac Motors In General (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案に係わる電力制御回路の一実
施例を示す回路図、第2図は低域通過フイルタの
特性を示す図、第3図は各電源周波数におけるト
リガ・タイミングを説明するために示す図、第4
図、第5図はそれぞれこの考案の他の実施例を示
す回路図、第6図は従来の電力制御回路を示す回
路図である。 10,40…交流電源、11,47…モータ、
12…トライアツク、17…PUT、22,41
…低域通過フイルタ、48…サイリスタ。
Figure 1 is a circuit diagram showing an embodiment of the power control circuit according to this invention, Figure 2 is a diagram showing the characteristics of a low-pass filter, and Figure 3 is a diagram for explaining the trigger timing at each power frequency. Figure shown, 4th
5 are circuit diagrams showing other embodiments of this invention, and FIG. 6 is a circuit diagram showing a conventional power control circuit. 10,40...AC power supply, 11,47...motor,
12...Triack, 17...PUT, 22,41
...Low pass filter, 48...Thyristor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 交流電源を整流する整流手段と、この整流手段
の整流出力よりトリガ信号を生成するトリガ信号
生成手段と、前記交流電源に接続され前記トリガ
信号生成手段より出力されるトリガ信号によつて
負荷に対する電力を制御する制御整流手段と、前
記交流電源の周波数に応じたレベルの信号を生成
し、この信号により前記トリガ信号生成手段のト
リガ出力タイミングを変化する低域通過フイルタ
とを具備したことを特徴とする電力制御回路。
A rectifying means for rectifying an AC power source, a trigger signal generating means for generating a trigger signal from the rectified output of the rectifying means, and a trigger signal connected to the AC power source and output from the trigger signal generating means to generate power to the load. and a low-pass filter that generates a signal with a level corresponding to the frequency of the AC power source and changes the trigger output timing of the trigger signal generation means based on this signal. power control circuit.
JP1986184528U 1986-11-29 1986-11-29 Pending JPS6390996U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986184528U JPS6390996U (en) 1986-11-29 1986-11-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986184528U JPS6390996U (en) 1986-11-29 1986-11-29

Publications (1)

Publication Number Publication Date
JPS6390996U true JPS6390996U (en) 1988-06-13

Family

ID=31132291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986184528U Pending JPS6390996U (en) 1986-11-29 1986-11-29

Country Status (1)

Country Link
JP (1) JPS6390996U (en)

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