JPS6388917A - Semiconductor logic circuit - Google Patents

Semiconductor logic circuit

Info

Publication number
JPS6388917A
JPS6388917A JP61234931A JP23493186A JPS6388917A JP S6388917 A JPS6388917 A JP S6388917A JP 61234931 A JP61234931 A JP 61234931A JP 23493186 A JP23493186 A JP 23493186A JP S6388917 A JPS6388917 A JP S6388917A
Authority
JP
Japan
Prior art keywords
output
logic circuit
vcc
resistor
highest potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61234931A
Other languages
Japanese (ja)
Other versions
JPH0644707B2 (en
Inventor
Masahiko Arimura
有村 政彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61234931A priority Critical patent/JPH0644707B2/en
Publication of JPS6388917A publication Critical patent/JPS6388917A/en
Publication of JPH0644707B2 publication Critical patent/JPH0644707B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a stable input threshold characteristic by inserting a resistor between a highest potential terminal and the collector terminal of an output transistor (TR) in an ECL logic circuit so as to suppress the output ringing. CONSTITUTION:In the ECL logic circuit, a resistor R is provided between the highest potential terminal VCC and the collector of the output TR Q. Then the output waveform when the output is switched from low to high level is the waveform to which ringing is suppressed. Thus, the input threshold characteristic with respect to the standards of input/output voltage is stabilized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ECL型論理回路において、出力トランジス
タが発生するノイズ電圧を低減する回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for reducing noise voltage generated by an output transistor in an ECL type logic circuit.

〔従来の技術〕[Conventional technology]

従来より、ECL型論理回路で、特に多ビツト系の論理
回路においては、最高電位端子(以下Vccと略す)と
出力トランジスタのコレクタ端子(以下Vccと略す)
を分離し、ICのバーケッジに取シ出す方法が取られて
いる。これは、パーケッジのリードとボンディングワイ
ヤが持つインダクタンスに出力トランジスタがスイッチ
ングする際、過渡電流が流れる為に発生するノイズ電圧
をVccが直接影響を受けないようにする為である。
Conventionally, in ECL type logic circuits, especially multi-bit logic circuits, the highest potential terminal (hereinafter abbreviated as Vcc) and the collector terminal of the output transistor (hereinafter abbreviated as Vcc) have been used.
A method has been adopted in which the IC is separated and taken out to the IC storage. This is to prevent Vcc from being directly affected by the noise voltage generated due to the flow of transient current when the output transistor switches in the inductance of the package lead and bonding wire.

第2図は、従来より用いられるECL回路である。第3
図は、出力トランジスタQがスイッチングする際の電流
の動きと負荷及び寄生のインダクタンスを示す。第2図
において、入力信号■xNがLotvからHighlC
切換ったとすると、工。は馬から流れていたものが、R
2に切換シ、出力トランジスタのペース電位はLowか
らHighに遷移する。この時、第2図においてVCC
端子に存在するインダクタンスL1に流れる電流の変化
量は、無視できる程度に少ないがs Ltにはトランジ
スタが負荷RT及qGに流し込む過渡電流が流れる。
FIG. 2 shows a conventionally used ECL circuit. Third
The figure shows the current behavior and the load and parasitic inductances as the output transistor Q switches. In Fig. 2, the input signal xN is from Lotv to HighC
If you switch, then What was flowing from the horse was R.
2, the pace potential of the output transistor transitions from Low to High. At this time, in Figure 2, VCC
Although the amount of change in the current flowing through the inductance L1 present at the terminal is negligibly small, a transient current that the transistor flows into the loads RT and qG flows through sLt.

一方、高速動作を特徴とするECL型論理回路において
は、特に出力のLowからHighへの立上シ時間は非
常に小さく、急峻である。
On the other hand, in an ECL type logic circuit characterized by high-speed operation, the rising time of the output from Low to High is extremely short and steep.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の回路では、出力は急峻な立上シ特性をも
っているおシ、これは立上シ時のオーバーシーートとな
シ、それに起因するリンギング、或いは発振を引き起す
ことになる。このリンギングは、 VccとVcc人端
子端子絡することによシ、抑えることができるが、前述
のようにインダクタンスL、を流れる電流が、Vcc端
子に直接ノイズ電圧を与えることになシ、このノイズ電
圧の為に入力しきい値特性が著しく悪くなるという欠点
がある。
In the above-mentioned conventional circuit, the output has a steep rise characteristic, which causes over-sheeting at the time of rise, resulting in ringing or oscillation. This ringing can be suppressed by connecting the Vcc and Vcc terminals, but as mentioned above, the current flowing through the inductance L does not directly apply the noise voltage to the Vcc terminal, and this noise There is a drawback that the input threshold characteristics are significantly deteriorated due to the voltage.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の回路は、最高電位端子と出力トランジスタの端
子を有するBCL型論理回路において、該最高電位端子
と該出力トランジスタのコレクタ端子の間に抵抗を有し
ていることを特徴とする。
The circuit of the present invention is a BCL type logic circuit having a highest potential terminal and an output transistor terminal, and is characterized in that a resistor is provided between the highest potential terminal and the collector terminal of the output transistor.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は、本発明の具体的実施例であり、最高電位端子
と出力トランジスタのコレクタの間が抵抗Rで接続され
ている。第4図−(a)は出力がLowからHighに
スイッチングする時の出力波形である。
FIG. 1 shows a specific embodiment of the present invention, in which a resistor R is connected between the highest potential terminal and the collector of the output transistor. FIG. 4-(a) shows the output waveform when the output is switched from Low to High.

実線は従来例、即ちリンギングが見られる出力波形を示
し、 Vcc−VCCA間を直接短絡した場合、或は抵
抗を介して接続することにより、リンギングが抑えられ
た出力波形を点線で示す、第4図−(b)は、入出力電
圧の規格に対する入力しきい値特性を示す。従来例、即
ちVcc −VccA間が接続されてない場合、出力の
スイッチングによるノイズ電圧は、内部回路の動作に影
響しないので、入力しきい値特性は、安定している。こ
れを実線で示す。
The solid line shows the conventional example, that is, the output waveform in which ringing is observed, and the dotted line shows the output waveform in which ringing is suppressed when Vcc and VCCA are directly shorted or connected through a resistor. Figure (b) shows the input threshold characteristics with respect to the input/output voltage standards. In the conventional example, that is, when Vcc and VccA are not connected, the noise voltage due to output switching does not affect the operation of the internal circuit, so the input threshold characteristic is stable. This is shown as a solid line.

一方、VCC−VCCAを直接短絡した場合、ノイズ電
圧の為、特にVZH側の特性が著しく悪くなり、規格に
に対するマージンが十分確保できなくなる。これを点線
で示す。図中の一点鎖線がVcc −VccA間を抵抗
を介して接続した場合の特性である。Vcc −Vcc
λ間短絡の場合に比べて、特性が改善され規格に対する
マージンも確保でき、製造ばらつき等に対しても十分規
格を保障することができる。
On the other hand, if VCC-VCCA is directly short-circuited, the noise voltage will cause the characteristics, especially on the VZH side, to deteriorate significantly, making it impossible to secure a sufficient margin against the standard. This is shown by the dotted line. The dashed-dotted line in the figure shows the characteristics when Vcc and VccA are connected through a resistor. Vcc −Vcc
Compared to the case of a short circuit between λ, the characteristics are improved, a margin for the standard can be secured, and the standard can be sufficiently guaranteed against manufacturing variations.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明はECL型論理回路におい
て、最高電位端子と出力トランジスタのコレクタ端子の
間に抵抗を挿入することばより、出力のリンギングを抑
え、かつ安定した入力しきい値特性を得ることができる
As explained above, the present invention suppresses output ringing and obtains stable input threshold characteristics by inserting a resistor between the highest potential terminal and the collector terminal of the output transistor in an ECL type logic circuit. be able to.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の回路図、第2図は、従来例の回路図
、第3図は、第2図における電流動作を示す図、第4図
(a)は、従来例と本発明における出力動作波形、第4
図(blは、入出力電圧の規格に対する入力しきい値特
性を示す図である。 ”it几2・・・・・・抵抗。 7に(−VCcA 竿ゾ図 VEε (aン と6) 第4図
Fig. 1 is a circuit diagram of the present invention, Fig. 2 is a circuit diagram of a conventional example, Fig. 3 is a diagram showing current operation in Fig. 2, and Fig. 4 (a) is a diagram of the conventional example and the present invention. Output operation waveform at 4th
Figure (bl is a diagram showing the input threshold characteristics with respect to the input/output voltage standard. Figure 4

Claims (1)

【特許請求の範囲】[Claims] 最高電位端子と出力トランジスタのコレクタ端子を有す
るECL型論理回路において、該最高電位端子と該出力
トランジスタのコレクタの間が抵抗を介して、接続され
ていることを特徴とする半導体論理回路。
1. A semiconductor logic circuit having an ECL type logic circuit having a highest potential terminal and a collector terminal of an output transistor, wherein the highest potential terminal and the collector of the output transistor are connected through a resistor.
JP61234931A 1986-10-01 1986-10-01 Semiconductor logic circuit Expired - Lifetime JPH0644707B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61234931A JPH0644707B2 (en) 1986-10-01 1986-10-01 Semiconductor logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61234931A JPH0644707B2 (en) 1986-10-01 1986-10-01 Semiconductor logic circuit

Publications (2)

Publication Number Publication Date
JPS6388917A true JPS6388917A (en) 1988-04-20
JPH0644707B2 JPH0644707B2 (en) 1994-06-08

Family

ID=16978519

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61234931A Expired - Lifetime JPH0644707B2 (en) 1986-10-01 1986-10-01 Semiconductor logic circuit

Country Status (1)

Country Link
JP (1) JPH0644707B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5176069A (en) * 1974-12-26 1976-07-01 Fujitsu Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5176069A (en) * 1974-12-26 1976-07-01 Fujitsu Ltd

Also Published As

Publication number Publication date
JPH0644707B2 (en) 1994-06-08

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