JPS6381947A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a defective leakage among second layer patterns at a stepped section by a first layer pattern by forming a first pattern, shaping a non-doped semiconductor film for forming a second pattern, selectively doping an impurity and patterning the semiconductor film. CONSTITUTION:A non-doped polycrystalline silicon film is shaped onto the whole surface, an insulating film is formed onto the film, and a plurality of photo-resist patterns 5 having a predetermined shape are shaped onto the insulating film so as to be superposed on a first layer wiring 3. These photo-resist patterns 5 are isolated mutually along the direction that the wiring 3 extends, and formed in response to a plurality of regions containing sections subsequently functioning as one parts of a second layer wiring 6 in polycrystalline silicon films. The insulating film is etched, using the patterns 5 as masks, and an impurity such as phosphorus is doped selectively. The insulating film is removed through etching, and the polycrystalline silicon films are patterned, thus forming the second layer wiring 6 vertically crossing the first layer wiring 3.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device having a two-layer wiring structure. .

[Conventional technology]

For example, 256 bits (73CMO3EPROM (Er)
agabls and Programw＊abl
In order to prevent latch-up due to the formation of a parasitic thyristor structure, information is written into the memory cell using a p-channel MoS transistor formed from a polycrystalline silicon film provided on a SiO2 film. F for circuit
E'r (for example, Nikkei Microdevice, August 1985 issue, P, 73-P, 85).

The present inventor studied a method for manufacturing this 0MO3 EPROM. Although the following is not a publicly known technique, it is a technique studied by the present inventor, and its outline is as follows.

That is, when manufacturing a CMOSEPROM, the floating gate pattern in the memory cell part and the first layer wiring connected thereto are formed using a polycrystalline silicon film, and a film such as SiO□ film, for example, is formed on these surfaces by thermal oxidation. After forming an interlayer insulating film, a non-doped polycrystalline silicon film is formed on the entire surface.The first step is to form a non-doped polycrystalline silicon film on the surface of the region including the portion where the P-channel MoS transistor is to be formed. While covered with an insulating film, the resistance is lowered by diffusing, for example, phosphorus into this polycrystalline silicon film using this insulating film as a mask8.
Next, after removing the insulating film by etching, the polycrystalline silicon film is etched, for example, by reactive ion etching (R, I'
By patterning it into a predetermined shape using E), a word line in the memory cell section, a polycrystalline silicon film for forming a p-channel MOS)-transistor, and a second layer for connecting this transistor to a program potential VPP supply section are formed. Form wiring. This second layer wiring intersects with the -th layer wiring connected to the floating gate pattern.

In the above-mentioned technique, since the insulating film serving as an impurity diffusion mask is formed much wider than the p-channel MoS transistor, there is a portion where an undoped polycrystalline silicon film is present even above the -th layer wiring. Therefore, in order to form the second layer wiring, it is necessary to etch the non-doped polycrystalline silicon film in this portion.

[Problem that the invention seeks to solve]

However, the stepped portion caused by the first layer wiring after the formation of the interlayer R film often has an inverted tapered shape. Therefore, when etching the non-doped polycrystalline silicon film, Etching residues tend to occur along the lines, and this etching residue tends to cause leakage defects between the second layer wirings, which causes write defects.

An object of the present invention is to provide a technique that can prevent leakage defects between second-layer patterns at a stepped portion caused by the -th-layer pattern.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

An overview of one typical invention disclosed in this application is as follows.

That is, the step of forming a non-doped semiconductor film in the second patterning after forming the first pattern, and the step of forming a non-doped semiconductor film in the second pattern, which are separated from each other along the extending direction of the first pattern, and at least one of the second patterns. a step of selectively doping an impurity into the semiconductor film in a portion excluding a plurality of regions including a portion that will become a portion; and a step of forming the second pattern by patterning the semiconductor film. ing.

[For production]

According to the above-mentioned means, even if an etching residue is generated in the step portion caused by the first pattern during etching to form the second pattern, this etching residue is not continuous between a plurality of adjacent second patterns. Therefore, leakage defects between these second patterns can be prevented.

〔Example〕

Hereinafter, the configuration of the present invention will be described based on one embodiment with reference to the drawings.

In addition, in all the figures, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

FIG. 1 is a plan view showing the main parts of an 0MO8EFROM according to an embodiment of the present invention, FIG. 2 is an enlarged sectional view taken along line A-A in FIG. 1, and FIG. 3 is a B-- It is an enlarged sectional view along Bi.

As shown in FIGS. 1 to 3, first, an insulating film 2 such as a 5if2 film (not shown in FIG. 1) is formed on a semiconductor substrate 1 such as a silicon substrate, and
A first layer wiring 3 made of, for example, a polycrystalline silicon film doped with impurities is formed via this insulating film 2. In addition,
At this time, the bloating gate pattern (
(not shown) is also formed at the same time. Next, an interlayer insulating film 4 such as 5io2all, for example, is formed on the surface of the wiring 3 by thermal oxidation. After this thermal oxidation, as shown in FIG. 2 or 3, the stepped portion formed by the wiring 3 has a reverse tapered shape, and the wiring 3 is curved so as to be convex downward.

Next, after forming, for example, a non-doped polycrystalline silicon film on the entire surface, an insulating film (not shown) such as a 5-ins film is formed on this polycrystalline silicon film. Oily multiple photoresist patterns 5 (
1) is formed so as to overlap with the negative layer wiring 3. These photoresist patterns 5 are separated from each other along the direction in which the wiring 3 extends, and correspond to a plurality of regions including a portion of the polycrystalline silicon film that will later become a part of the second layer wiring 6. Form. Note that p-channel M for writing
A photoresist pattern (not shown) having a predetermined shape is also formed on the insulating film above the region including the oS transistor forming portion.

Next, the insulating film is etched using the photoresist pattern 5 as a mask. As a result, an insulating film having the same shape as the photoresist pattern 5 is formed.Next, after removing the photoresist pattern 5, using the insulating film as a mask, the polycrystalline silicon film is diffused with, for example, phosphorus. selectively doping with impurities to lower resistance. In this case, since no impurity is introduced into the polycrystalline silicon film below the insulating film, it remains undoped.

Next, after removing the insulating film by etching, the polycrystalline silicon film is patterned by, for example, RIE to form a second layer wiring 6 that intersects, for example, perpendicularly with the -th layer wiring 3. In this case, in the portion of the polycrystalline silicon film that is not doped with impurities (the portion corresponding to the photoresist pattern 5), the wiring 3 is etched during the etching, as in the technique studied by the present inventor. An etching residue 7 is generated at the stepped portion.

On the other hand, the etching rate of the n4 type low resistance portion doped with impurities in the polycrystalline silicon film is R
For example, when CF4 is used as an etching gas for IE, the etching rate is about twice that of non-doped polycrystalline silicon, and the etching rate is about twice that of non-doped polycrystalline silicon.
If s is used, it will be more than 10 times, so this rl
In the '-shaped portion, it is possible to prevent etching residue from occurring along the stepped portion due to the wiring 3. Therefore, even if etching residues 7 occur along the stepped portions of the interconnections 3 in the non-doped portion of the polycrystalline silicon film, these etching residues 7 form a plurality of adjacent second layer layers! Since the lines 6 are not continuous, leakage defects between adjacent lines 6 can be prevented. Therefore, it is possible to prevent writing failures due to leakage failures.

Although the invention made by the present inventor has been specifically explained above based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the gist of the invention. It is.

For example, the present invention can be applied to various semiconductor integrated circuit devices such as a one-chip microcomputer having an EPROM.

Note that, for example, as shown in FIG. 4, in the −th layer wiring 3,
By providing a protrusion 3a extending vertically to the outside of the photoresist pattern 5 and proceeding with the process using the photoresist pattern 5 in the same manner as in the above embodiment, the same effect as in the above embodiment can be obtained. can be obtained.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

That is, leakage defects between the second patterns can be prevented.

[Brief explanation of the drawing]

FIG. 1 shows a CMO8EPROM according to an embodiment of the present invention.
FIG. 2 is an enlarged sectional view taken along line A-A in FIG. 1; FIG. 3 is an enlarged sectional view taken along line B-B in FIG. 1. FIG. 4 is a plan view showing another example that can obtain the same effects as the embodiment of the present invention. In the figure, 1... Semiconductor substrate, 3... Wiring (first pattern), 4... Interlayer insulating film, 5... Photoresist pattern, 6... Wiring (second pattern), 7...
This is the rest of the etching. Figure 1

Claims (1)

[Claims] 1. Manufacture of a semiconductor integrated circuit device having a first pattern in a first layer and a second pattern in a second layer provided to intersect with the first pattern The method includes the steps of: forming a non-doped semiconductor film for forming the second pattern after forming the first pattern; forming the second pattern by selectively doping the semiconductor film with an impurity in a portion excluding a plurality of regions including at least a portion of the pattern; and patterning the semiconductor film. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the second pattern is a polycrystalline silicon wiring. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1 or 2, wherein the first pattern is a polycrystalline silicon wiring. 4. The method of manufacturing a semiconductor integrated circuit device according to any one of claims 1 to 3, wherein the semiconductor integrated circuit device is a CMOSEPROM.