JPS637643A - Wire bonder - Google Patents

Wire bonder

Info

Publication number
JPS637643A
JPS637643A JP61152518A JP15251886A JPS637643A JP S637643 A JPS637643 A JP S637643A JP 61152518 A JP61152518 A JP 61152518A JP 15251886 A JP15251886 A JP 15251886A JP S637643 A JPS637643 A JP S637643A
Authority
JP
Japan
Prior art keywords
wire
bonding
current
pad
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61152518A
Other languages
Japanese (ja)
Inventor
Akihiro Kubota
昭弘 窪田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61152518A priority Critical patent/JPS637643A/en
Publication of JPS637643A publication Critical patent/JPS637643A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/851—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector the connector being supplied to the parts to be connected in the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Abstract

PURPOSE:To facilitate the production control of wire bonding, by conducting current between wire and a die pad at the time when wire bonding to a bonding pad on a semiconductor element is finished, and judging the state of the first wire bonding based on the current conducting state. CONSTITUTION:When the first wire bonding is finished, a circuit from a wire (Au wire) 8 to a wire feeding part 10 through a bonding pad 3, a semiconductor element 2, a die pad (lead frame) 1A, and a current conduction checker 6 is closed, and a current can be conducted. Then, the current is conducted in the forward direction to a P-N junction in the semiconductor element 2, and the current conducting state is checked. Thus, whether the first bonding is excellently performed or the bonded part is separated or shorted can be judged in an on-line state.

Description

【発明の詳細な説明】 〔概要〕 ワイヤボンダーにおいて、半導体素子上のボンディング
パッドへのワイヤボンディングが終了した時点で、ワイ
ヤとグイパッド間に通電し、この通電状況により、第１
のワイヤボンディングの状況を判定しワイヤボンディン
グの工程管理を容易にする。[Detailed Description of the Invention] [Summary] In a wire bonder, when the wire bonding to the bonding pad on the semiconductor element is completed, electricity is applied between the wire and the Gui pad, and depending on this energization situation, the first
To facilitate wire bonding process management by determining the status of wire bonding.

〔産業上の利用分野〕[Industrial application field]

本発明はワイヤボンダーに係わり、詳しくは第１のワイ
ヤボンディングの接続状況を検査する機能を有するワイ
ヤボンダーに関する。The present invention relates to a wire bonder, and more particularly to a wire bonder having a function of inspecting the connection status of a first wire bond.

半導体装置の大部分のものは、半導体素子から外部リー
ドへ金（Ａｕ）線、アルミニウム（ＡＩ）線等の配ＶＡ
（ワイヤ）をワイヤボンダｉにより接続している。Most semiconductor devices have VA wiring such as gold (Au) wires or aluminum (AI) wires from the semiconductor element to the external leads.
(wires) are connected by wire bonder i.

このワイヤポンドの品質は、工程中の歩留りの低下だけ
でなく、製品になってからの断線やショート不良等の発
生に影響するので重要である。The quality of this wire pond is important because it not only reduces the yield during the process, but also affects the occurrence of disconnections, short circuits, etc. in the product.

現在のワイヤボンダーは殆どのものが自動化され、高速
でワイヤボンドが行われているので、細心の注意をはら
った充分な工程管理を実施する必要がある。Most of the current wire bonders are automated and wire bonding is performed at high speed, so it is necessary to carry out sufficient process control with utmost care.

しかし、従来のワイヤボンダーは、工程中にオンライン
でボンディング状況を把握する構造となっていないため
、抜取りによりチエツクしている。However, conventional wire bonders do not have a structure to check the bonding status online during the process, so they are checked by sampling.

しかし、この方法では突発的に発生する異常、散発的に
発生する異常に対して機敏に対応がとれないため品質管
理運用面で難がある。However, this method is difficult in terms of quality control operations because it is not possible to quickly respond to abnormalities that occur suddenly or sporadically.

本発明はボンディング中の剥がれを工程中に常時監視す
ることにより、上記欠点を改善しようとするものである
。The present invention aims to improve the above drawbacks by constantly monitoring peeling during bonding during the process.

〔従来の技術〕[Conventional technology]

第４図は従来例におけるワイヤボンダー構成模式図であ
る。FIG. 4 is a schematic diagram of the configuration of a wire bonder in a conventional example.

この図において、１Ａはダイパッドで、この上に半導体
素子２を接着載置する。また１Ｂは外部リードで、ダイ
パッド１Ａと共にリードフレームと称する１枚の金属板
を打ち抜き加工したものを構成している。従ってワイヤ
ボンディング時点ではダイパッド１Ａと外部リード１Ｂ
は電気的に接続されている。In this figure, 1A is a die pad, on which the semiconductor element 2 is adhesively placed. Further, 1B is an external lead, which together with the die pad 1A is formed by punching out a single metal plate called a lead frame. Therefore, at the time of wire bonding, die pad 1A and external lead 1B
are electrically connected.

半導体素子２にはＡＩ電極のボンディングバンド３があ
り、この部分でＡｕ線のワイヤ８を接着するをキャピラ
リー４を通した後、このキャピラリー４の下でワイヤ８
に電気アークによりボールを形成し、このボールをキャ
ピラリー４で引っ掛けて、予めリードフレームを加熱す
ることにより温度が上がったボンディングバンド３に押
しつけて熱圧着して、第１のボンディングを行い、つい
でキャピラリー４を移動して外部リード１Ｂの上に熱圧
着して第２のボンディングを行う。ついでワイヤをクラ
ンプしてキャピラリー４を上げることによりワイヤを接
着点よりスプール側で切り離し、ついで又次のボンディ
ングのためのボールを形成する。これがワイヤボンダー
の主要動作である。The semiconductor element 2 has a bonding band 3 for the AI electrode, and after passing the Au wire 8 through the capillary 4 through this part, the wire 8 is bonded under the capillary 4.
A ball is formed by an electric arc, this ball is hooked by the capillary 4, and is pressed against the bonding band 3 whose temperature has been raised by heating the lead frame in advance to perform the first bonding. 4 is moved and thermocompressed onto the external lead 1B to perform second bonding. Then, by clamping the wire and raising the capillary 4, the wire is separated from the bonding point on the spool side, and then a ball for the next bonding is formed. This is the main operation of the wire bonder.

このワイヤボンディングの品質の確認は、作業中におけ
る抜取りにより、目視外観検査と引張りテストによる接
着強度検査によっている。The quality of this wire bonding is confirmed by sampling samples during work, visual appearance inspection, and adhesive strength inspection using a tensile test.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来例のワイヤボンダーは、ボンディングを行うだけで
、チエツク機能を備えておらず、作業の工程品質の管理
を製品抜取り検査法によっているため、抜取り時点と検
査完了時点のタイムラグがあり、ために不良原因排除が
遅れる欠点を有している。Conventional wire bonders only perform bonding and do not have a check function, and the process quality of the work is managed using the product sampling inspection method, so there is a time lag between the sampling point and the inspection completion point, which can lead to defects. It has the disadvantage that eliminating the cause is delayed.

ワイヤボンディングの品質のうち、特に第１のボンディ
ングのそれは４種々の要因により変動し易いので、これ
の管理は重要である。Among the quality of wire bonding, especially that of the first bonding, it is easy to fluctuate due to four different factors, so management of this quality is important.

第１のボンディングの剥がれの原因は、主に素子電極製
造工程のバラツキによるボンディングパッド異常や、有
機性接着剤を用いて素子をパッケージにマウントすると
き発生する低分子ガスのボンディングパッド表面への付
着等で、突発的に発生する。The first cause of bonding peeling is mainly bonding pad abnormalities due to variations in the device electrode manufacturing process, and adhesion of low-molecular gas to the bonding pad surface that occurs when mounting the device on the package using organic adhesive. etc., occur suddenly.

また、散発的にボンディング剥がれ不良が発注した場合
、従来の抜取りチエ・７りではその発生頻度が把握出来
ず、ロフト全体の品質管理（品質レベル判定、レベル維
持管理、データ集計、対策）運用面で難がある。In addition, when orders are made for sporadic bonding peeling defects, the frequency of occurrence cannot be ascertained using conventional sampling checks and inspections, and the operational aspects of quality control (quality level determination, level maintenance management, data aggregation, and countermeasures) for the entire loft There is a problem.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点の解決は、ダイパッド（１Ａ）上に接着され
た半導体素子（２）上のボンディングパッド（３）に第
１のボンディングによりワイヤ（８）を接続し、更にこ
のワイヤ（８）を第２のボンディングにより外部リード
（１Ｂ）に接続するワイヤボンダーにおいて、−方でボ
ンディングパ・７ド（３）に電気的に接続し、他方で前
記ワイヤ（８）のワイヤ供給部（１０）でワイヤ（８）
に電気的に接続された通電チェッカー（６）を有し、こ
の通電チェッカー（６）により、第１のボンディングが
終了した時点に、ワイヤ（８）からダイパッド（１Ａ）
に対して通電し、その通電状況を検査する本発明による
ワイヤボンダーにより達成される。The solution to the above problem is to connect the wire (8) to the bonding pad (3) on the semiconductor element (2) bonded on the die pad (1A) by first bonding, and then connect this wire (8) to the bonding pad (3) on the semiconductor element (2) bonded on the die pad (1A). In the wire bonder that connects to the external lead (1B) by bonding No. 2, the - side is electrically connected to the bonding pad No. 7 (3), and the wire supply section (10) of the wire (8) is connected to the wire on the other side. (8)
The energization checker (6) detects whether the wire (8) is connected to the die pad (1A) when the first bonding is completed.
This is achieved by the wire bonder according to the present invention, which energizes the wire and inspects the energization status.

〔作用〕 本発明によると、第１のワイヤボンディングが終了した
時点で、ワイヤ８よりボンディングパ、７ド３、半導体
素子２、グイパッドＬＡ、通電チェッカー６、ワイヤ供
給部１０に至る回路が閉じて通電可能となるので、半導
体素子２の有するＰ−Ｎ接合に対して順方向に通電し、
その通電状況をチエツクすることにより、第１のボンデ
ィングが良好になされているか、或いは剥がれているが
、或いはショートしているか等をオンライン的に判定す
ることが可能となる。[Operation] According to the present invention, when the first wire bonding is completed, the circuit from the wire 8 to the bonding pad 3, the semiconductor element 2, the energization checker 6, and the wire supply section 10 is closed. Since current can be applied, current is applied in the forward direction to the P-N junction of the semiconductor element 2,
By checking the energization status, it is possible to determine online whether the first bonding is properly performed, peeled off, or short-circuited.

〔実施例〕〔Example〕

第１図は本発明におけるワイヤボンダー構成模式図であ
る。FIG. 1 is a schematic diagram of the wire bonder configuration according to the present invention.

この図において、第４図と同じ名称のものは同じ符号で
示す。In this figure, parts with the same names as in FIG. 4 are designated by the same reference numerals.

この図において、グイパッド１ＡＯ上には半導体素子２
が接着載置される。半導体素子２には複数のＡ１％ｉ極
のボンディングパッド３があり、この部分でＡｕ線のワ
イヤ８を接着する、第１のボンディングを行う。ボンデ
ィング動作自体は従来例に述べた方法と全く同じで、キ
ャピラリー４を通って来たワイヤ８の先にボールを形成
し、これをボンディングパッド３に熱圧着により接着す
る。In this figure, there is a semiconductor element 2 on the Guipad 1AO.
is glued and placed. The semiconductor element 2 has a plurality of A1% i-pole bonding pads 3, and first bonding is performed to bond the Au wire 8 to these portions. The bonding operation itself is exactly the same as the method described in the conventional example, in which a ball is formed at the tip of the wire 8 passing through the capillary 4, and this is bonded to the bonding pad 3 by thermocompression bonding.

ワイヤ供給部１０は、この中にワイヤ８を巻いたワイヤ
スプール５を収納すると同時に、スイッチング機能を持
つ通電チェッカー６に電気的に接続される。The wire supply unit 10 stores therein a wire spool 5 with a wire 8 wound therein, and is electrically connected to an energization checker 6 having a switching function.

更に、通電チェッカー６はグイパッド１Ａに接続され、
又ＭＰＵ　（マイクロ　プロセンシングユニット）７に
も接続される。Furthermore, the energization checker 6 is connected to the Guipad 1A,
It is also connected to an MPU (micro processing unit) 7.

ＭＰＵ７は通電チェッカー６を通じてワイヤボンダー本
体とつながっていて、通電時間、通電方向を各ボンディ
ングパッド毎に設定し、通電状態をチエツクして判定し
、判定データを集計し、さらにワイヤボンダーの動作を
制御する機能を有する。The MPU 7 is connected to the wire bonder body through the energization checker 6, and sets the energization time and direction for each bonding pad, checks and determines the energization state, aggregates the determination data, and further controls the operation of the wire bonder. It has the function of

第２図（ａ）　、　（ｂ）は本発明におけるボンディン
グチエツク状況図である。FIGS. 2(a) and 2(b) are diagrams showing the state of the bonding check in the present invention.

第２図（ａ）はボンディングＯＫの状態を示す図である
。FIG. 2(a) is a diagram showing a state in which bonding is OK.

第１のボンディングが終了し、第２のボンディング位置
に移っている状態で、第１のボンディングは接着充分で
良好であるため、通電可能の状態となる。但し半導体素
子はＰ−Ｎ接合を含んでいるので、これに対して順方向
に電流Ｉを流し、この電流■の流れ方をＭＰＵ７で判定
する。When the first bonding is completed and the first bonding is moved to the second bonding position, the first bonding is sufficiently bonded and is good, so that it becomes possible to conduct electricity. However, since the semiconductor element includes a PN junction, a current I is caused to flow in the forward direction through this, and the MPU 7 determines how the current 2 flows.

第２図（ｂ）はボンディングＮＧ（剥Ｍ）の状態を示す
図である。FIG. 2(b) is a diagram showing a state of bonding NG (peeling M).

第１のボンディングが成功せず、ワイヤのボールがボン
ディングパッド３にうまく接着せず、剥がれてキャピラ
リー４の先についたまま移動している所を示す。この場
合は回路が閉じないので通電ＯＦＦとなり、ＭＰＵ７は
電流［＝０と判定する。The first bonding was not successful, and the ball of wire did not adhere well to the bonding pad 3, was separated, and moved while remaining attached to the tip of the capillary 4. In this case, since the circuit does not close, the current is turned off, and the MPU 7 determines that the current is [=0].

第３図は本発明における通電チエツク判定の一例を示す
。FIG. 3 shows an example of energization check determination in the present invention.

この図はＰ−Ｎ接合の順方向のＶ−１特性図である。This figure is a forward V-1 characteristic diagram of a PN junction.

この図において、例えば、０．６■を順方向に５０〜５
００μｓｅｃ印加する。このとき流れる電流値ｒの値に
より １　　＜　　０．１ｍＡ　　　　　ＮＧ（剥がれ不良）
１　　＝　　０．１〜０．３　　ｍＡ　　ＯＫｌ　　＞
　　０．３ｍＡ　　　　ＮＧ（ショート不良）と判定す
る。ここでショート不良は、ボンディングパッドの下の
絶縁膜を破壊し、その下のＡＩ配線あるいはポリＳｉ膜
と短絡する等して規定以上の電流■が流れるものである
。In this figure, for example, 0.6■ is 50 to 5 in the forward direction.
Apply for 00 μsec. Depending on the current value r that flows at this time, 1 < 0.1mA NG (peeling defect)
1 = 0.1~0.3 mA OKl>
Determined as 0.3mA NG (defective short circuit). Here, a short-circuit defect is one in which the insulating film under the bonding pad is destroyed and a short circuit occurs with the underlying AI wiring or poly-Si film, causing a current (2) exceeding the specified value to flow.

この判定条件は１つの品種にあっても個々のボンディン
グパッドで異なる場合が多いので、それぞれ適した値と
することは勿論である。Since this determination condition often differs depending on the individual bonding pads even in one product type, it goes without saying that it should be set to an appropriate value for each bonding pad.

このようにすることにより、ボンディング作業時に、そ
の場でボンディング状況が把握出来るので、極めて品質
管理が容易となる。By doing this, the bonding situation can be grasped on the spot during the bonding operation, making quality control extremely easy.

実施例では、リードフレームを使用したグイパッドと外
部リードが電気的に接続されているものについて説明し
たが、これが切り離された構造のもの、即ちセラミック
パッケージ型等のワイヤボンディングにおいても応用出
来ることは勿論である。In the example, we have explained a case where the lead frame is used to electrically connect the lead pad and the external lead, but it goes without saying that it can also be applied to a structure in which this is separated, that is, wire bonding of a ceramic package type, etc. It is.

また、ワイヤ材料はＡｕ線であろうと、Ａｌ線であろう
と本発明は適用可能である。Furthermore, the present invention is applicable regardless of whether the wire material is Au wire or Al wire.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明によると第１のワイ
ヤボンディングが終了した時点で、ワイヤとグイパッド
間に通電し、このときの通電状況によりポンディングの
良否、更に剥離不良、ショート不良等不良の内容まで検
出し、第１のポンディングの品質管理を即時且つ詳細に
行うことが可能となる。As explained in detail above, according to the present invention, when the first wire bonding is completed, electricity is applied between the wire and the Gui pad, and depending on the current application status, the bonding is determined to be good or not, and further defects such as peeling defects, short circuit defects, etc. It becomes possible to detect even the contents of the first bonding and perform quality control of the first bonding immediately and in detail.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明におけるワイヤボンダー構成模式図、 第２図（ａ）　、（ｂ）は本発明におけるボンディング
チエツク状況図、 第３図は本発明における通電チエツク判定の一例、 第４図は従来例におけるワイヤボンダー構成模式図であ
る。 この図において、 １Ａはグイパッド（リードフレーム）、１Ｂは外部リー
ド（リードフレーム）、２は半導体素子、 ３はボンディングパッド、 ４はキャピラリー、 ５はワイヤスプール、 ６は通電チェッカー１ ７はマイクロプロセッシングユニソト （ＭＰＵ）、 ８はワイヤ（Ａｕ線）、 １０はワイヤ供給部 ７ｑゝ・４６°３月（二お１邦ワイＸ不゛シヌ゛二序肯
）９裳ｐ之テＮ、Ｇロチ　１　呟　　　　　　゛ ７Ｊ”ｆｋ’７１　ｉ二、Ａ’７３　Ｊ”　”ｙ７−（
ン／”　ｆ　エ□ソ７　ＸＩ、３Ｘｉｌ千　２　にFigure 1 is a schematic diagram of the wire bonder configuration according to the present invention, Figures 2 (a) and (b) are bonding check status diagrams according to the present invention, Figure 3 is an example of energization check determination according to the present invention, and Figure 4 is a conventional It is a wire bonder configuration schematic diagram in an example. In this figure, 1A is a lead pad (lead frame), 1B is an external lead (lead frame), 2 is a semiconductor element, 3 is a bonding pad, 4 is a capillary, 5 is a wire spool, 6 is a conduction checker 1, 7 is a microprocessing unit Soto (MPU), 8 is the wire (Au wire), 10 is the wire supply section 7q, 46° March (2, 1, 1, 2, 2, 3) 9, 9, 1, 1 Mutter ゛7J"fk'71 i2, A'73 J""y7-(
/” f E□So7 XI, 3Xil thousand 2 to

Claims (1)

【特許請求の範囲】 　ダイパッド（１Ａ）上に接着された半導体素子（２）
上のボンディングパッド（３）に第１のボンディングに
よりワイヤ（８）を接続し、更にこのワイヤ（８）を第
２のボンディングにより外部リード（１Ｂ）に接続する
ワイヤボンダーにおいて、 一方でボンディングパッド（３）に電気的に接続し、他
方で前記ワイヤ（８）のワイヤ供給部（１０）でワイヤ
（８）に電気的に接続された通電チェッカー（６）を有
し、 この通電チェッカー（６）により、第１のボンディング
が終了した時点に、ワイヤ（８）からダイパッド（１Ａ
）に対して通電し、その通電状況を検査する ことを特徴とするワイヤボンダー。[Claims] Semiconductor element (2) bonded on die pad (1A)
In a wire bonder that connects a wire (8) to the upper bonding pad (3) by first bonding and further connects this wire (8) to the external lead (1B) by second bonding, on the other hand, the bonding pad ( 3) and, on the other hand, an energization checker (6) electrically connected to the wire (8) at the wire supply section (10) of the wire (8), the energization checker (6) As a result, when the first bonding is completed, the wire (8) is connected to the die pad (1A
) and inspects the current status.
JP61152518A 1986-06-28 1986-06-28 Wire bonder Pending JPS637643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61152518A JPS637643A (en) 1986-06-28 1986-06-28 Wire bonder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61152518A JPS637643A (en) 1986-06-28 1986-06-28 Wire bonder

Publications (1)

Publication Number Publication Date
JPS637643A true JPS637643A (en) 1988-01-13

Family

ID=15542194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61152518A Pending JPS637643A (en) 1986-06-28 1986-06-28 Wire bonder

Country Status (1)

Country Link
JP (1) JPS637643A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02183033A (en) * 1989-01-09 1990-07-17 Ig Tech Res Inc House
US7654434B2 (en) 2005-03-21 2010-02-02 Infineon Technologies Ag Method, device and system for bonding a semiconductor element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02183033A (en) * 1989-01-09 1990-07-17 Ig Tech Res Inc House
US7654434B2 (en) 2005-03-21 2010-02-02 Infineon Technologies Ag Method, device and system for bonding a semiconductor element
DE102005012992B4 (en) * 2005-03-21 2014-01-02 Infineon Technologies Ag Method, bonding device and system for bonding a semiconductor element

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