JPS6369350A - Serial data processor - Google Patents

Abstract

PURPOSE:To contrive the improvement of the processing efficiency by allowing an output circuit to output a reception acknowledge signal (ACK) to a data line when the reception of a serial data on the data line is finished. CONSTITUTION:when a 1st serial data processor 100 has only to receive a reception data and it is not required for error check and data processing or the like after the reception, the software writes '0' to an ACK output selection flag 116. On the other hand, when it is required to apply error check and data processing or the like in a data processing section 103 after the reception, the software writes '1' to the ACK output selection flag 116. With the ACK output selection flag 116 set to '1', an ACK output circuit 114 outputs the reception acknowledge signal 122 when a reception signal 120 outputted from a serial clock control circuit 113 is at '1', and outputs the reception acknowledge signal 122 with the ACK output selection flag 116 set to '0' when a data processing end signal 121 reaches '1', by the control of the ACK write signal 119 outputted from the data processing section 103.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a serial data processing device that transmits and receives data in 7 reals in synchronization with a single 7 real clock.
In particular, the present invention relates to a serial data processing device that performs data reception confirmation processing and includes five circuits. [Prior art] Using one clock line and one data line,
A serial data processing device that serially transfers data bit by bit between SI chips will be described with reference to FIG. The first serial data processing device 400 includes a shift register 40, a serial clock generation circuit 402, a data processing section 403.7, a real clock, and a cross flag 405. Serial data terminal 406゜Serial black terminal 407
Contains. Shift register 401. Data processing section 4
03. The serial clock and cross flags 405 are interconnected (by an internal data bus 408). The data processing unit 403 has the functions of writing transmission data to the shift register 401 via the internal data bus 408, reading reception data from the shift register 401, and setting and clearing the serial clock and cross flag 405. There is. The shift register 401 is connected to a serial data terminal 406 via a line driver 410 for driving a serial data line 440, and the serial data terminal 406 is connected to the serial data line 440. serial data line 44
0 is also connected to the shift register 401 via the line buffer 409, and the 0 clear generator circuit 402 is connected to the serial clock terminal 407 via the clock driver 411. The serial clock/cross flag 405 is a flag for determining the serial clock supply source, and by setting this flag, the present clear data processing device becomes the serial clock supply source (that is, master mode). At this time, the clock driver 411 is controlled to select the output of the serial clock/return generation circuit 402, and at the same time output the serial clock/return obtained by the serial clock/return generation circuit 402 from the serial clock/return terminal 407. . On the other hand, when the serial clock flag 405 is cleared, the serial data processing device enters a slave mode in which it receives the serial clock signal and performs transmission/reception processing. , ri will be input. Serial clock, serial clock selected according to the state of the cross flag 405. The register is also used as a shift clock for the /store register 401. The second serial data processing device 420 has the same configuration as the first 7 real data processing device 400, and has an internal bus 42.
8, a shift register 421, a serial clock generator circuit 422, and a serial clock generator circuit 422. Data processing unit 423. It includes a serial clock and cross flag 425, and has seven real data terminals 426 and a serial clock terminal 427 as external terminals. Data processing unit 423 shift register 4
Process of writing transmission data to 21, 7 foot register 42
Processing to read received data from 1 and serial clock,
The set flag 425 is set and cleared. The shift register 421 is connected to the serial data line 4.
Through a line driver 430 for driving 40,
7 real data terminal 426, and serial data terminal 426 is connected to serial data line 440. The serial black and white generator circuit 422 is a black and white driver 4.
It is connected to a serial clock terminal 427 via a serial cable 31. The flag 425 is set when the real data processing device 420 becomes a master, and is reset (cleared) when it becomes a slave. The 7 real data terminals 406 and 7 real data terminals 407 of the first serial data processing device 400 are connected to the second serial data processing device 42 through a single serial data line 440 and a single serial data line 427.
0 serial data terminal 426 and serial clock terminal 427, respectively.

[There is. Next, referring to FIG. 9, the first 7 real data processing unit f1
Synchronization between the serial data on the 7 real data line 440 and the serial clock on the serial clock line 441 when successively transferring 8 bits of 7 real data from the 400 to the second serial data processing device 420 Explain the relationship. Here, the serial clock flag 405 of the first 7 real data processing device 400 is set, and this is set as the serial clock supply source (master). Real black, Kutosu flag 425 reissue. and treat it as a slave. The serial clock and Cryno 441 maintain a high level during non-transfer. When the data processing unit 403 transfers the transmission data to the shift register 401 via the internal data bus 408 at timing 'II, the serial clock generation circuit 402 starts generating a serial clock at timing 11. Serial black, terminal 407
The clock signal is sent out on the 7 real clock line 441 via the real clock line 441. Shift register 40] is a serial clock. Serial clock generated from the serial clock generation circuit 402. The falling edge of the shift register 401 performs a 1-bit, 7-bit operation in synchronization with the digital tl, and outputs the 1-bit and 7 bits of the final stage of the shift register 401 to the clear data terminal via the write/driver 4]0. 4
06 to the serial data rhino 440. Continuing, the register 401 is the serial clock, the falling edge of the serial clock, and the tse tse f? *t,,t
The shift operation is repeated in synchronization with each timing of 11ej13*"1istl?, and the pits shifted to the final stage of the shift register 401 are sequentially transferred to the clear data terminal 4.
06 to 7 real data lines 440. The second 7 real data processing device 420, which is the receiving side,
The serial clock line 441 synchronizes the serial clock signal input via the serial terminal 427 with the serial clock signal, the serial clock signal, and the serial clock input via the serial terminal 427.
The first 1 bit above is shifted into the first stage of the shift register 421 via the serial data terminal 426. Continuing, t4・t-yu t$・tl・, tl snow-h
In synchronization with the timing of 4@F-, subsequent pits serially transferred via the serial data line 440 are sequentially shifted into the shift register 421. tl. When the reception of the 8-bit data is completed at the timing of , the data processing unit 423 reads out the 8-bit data input into the shift register 421 via the internal data bus 428 and processes the data. The #th serial data processing device suspends the transmission process for a predetermined period during which the data processing related to serial data reception in the second serial data processing device will be completed, and then starts the next transmission process again. [Problems to be Solved by the Invention] The above-mentioned second serial data processing device has 8 pins and 8 pins (
Here, after receiving 1 byte of serial data, a reception confirmation signal is not sent to the first serial data processing device. Therefore, even if some abnormality occurs on the receiving side during the transfer of consecutive serial data of a plurality of bytes and the receiving side wants to cancel the reception, there is no means to notify the sending side of the rejection of reception. Therefore, in order to solve this problem, when the receiving side finishes processing the received data, it is necessary to output a reception confirmation signal to the transmitting side by software processing. However, Jin's method has a major drawback in that the receiving side must create a reception confirmation signal through software processing every time one byte is received, which significantly reduces the processing efficiency of the CPU. [Means for Solving the Problems] The serial data processing device of the present invention includes an output circuit that outputs a reception confirmation signal to the data line, and a first signal that notifies the output circuit that reception of serial data has ended. a circuit that generates a second signal to notify that processing of the received data has been completed; and a reception confirmation signal output selection flag that controls output of the reception confirmation signal;
The reception confirmation signal is output in synchronization with the first signal or the second signal based on the state trap of the reception confirmation signal selection flag. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a serial communication system using a first embodiment of the present invention. The first 7 real data processing device 100 is a shift register 1o]. Serial black and white generation circuit 1o2. Data processing unit 103
, serial clock, cross flag 1o5° serial data terminal 106. Serial Kuro, Ryuko】07. Internal data bus 1o8. Linepa, 7A 109. Line driver 11o, serial clock control circuit 113. Receipt confirmation signal (hereinafter referred to as ACK) detection circuit 104. ACK output times% 114 degrees, driver 111. ACK detection flag 1]5゜ACK output selection flag 116. and an ACK output driver 112. Of these, shift register 2
0], y real black, ri generation circuit 102. y'-event processing unit 103. Serial black, shoes flag] 05. Serial data terminal 106. Serial clock terminal 107.
Internal data bus 1o8. Since the functions of the driver 7 and the fiber 109 are the same as those shown in FIG. 8, a detailed explanation will be omitted here, and the functions of the other components will be explained below. The serial clock control circuit 1]3 outputs an ACK nanopulling signal [17]. This ACK sampling signal 117 becomes active after receiving data of a predetermined length.

[, used to specify the Sangrinob period of the acknowledgment signal. ACK output circuit 114 includes an ACK output selection flag 116. If the first serial data processing device 100 only needs to receive the received data and does not need to perform error checking, data processing, etc. after receiving the data, the software can
Write 'O' to the output selection flag 1/6. - If there is a need for error checking, data processing, etc. in the data processing unit/03 after reception, the software will
Write 'l' in the K output selection flag 116. When the ACK output selection flag 116 is 11m, the ACK output circuit 114 outputs a reception confirmation signal 22 when the reception signal 120 output from the serial clock control circuit 113 becomes @1"K, and outputs an ACK output. Selection flag 116 is 10"
In this case, the data processing end signal 121 is output under the control of the ACK write signal 119 which is also output by the data processing unit 103.
When the number reaches 111, a reception confirmation signal 122 is output. ACK detection circuit 104 includes an ACK detection flag 115. The ACK detection flag 115 is set when it is confirmed that a reception confirmation signal, which will be described later, is output on the serial data line [60] under the control of the ACK sampling signal [7]. The data processing unit 103 uses an ACK detection flag 115.
can be read out via the internal data bus 108, and the ACK detection flag 115 is cleared in synchronization with the start of serial transmission. The line driver 110 is a driver for driving the serial data rhino 160.
Controlled by ACK detection circuit 104. The second serial data processing device 130 includes shift registers 131 . Serial clock generation circuit 132, data processing section 133. Serial black, Kutusu flag] 35. Serial data terminal 136° Serial clock terminal 137
．． Internal data I (S) 38. Right bar, border 139. Line driver 140, clear black, rear control circuit 143
．． ACK detection circuit 134. ACK output circuit 144. Kuro, Ku driver 141. ACK detection flag 145°ACK
Output selection flag 146. and ACK output driver】4
Since the configuration and functions are the same as those of the first serial data processing device 100, detailed description thereof will be omitted here. Next, referring to FIG. 5, when the ACK output selection 7 lag 146 is Js and there is no need for error checking, data processing, etc. after data reception, the second serial data is output from the first 7 real data processing device 100. The synchronization relationship between the serial data on the 7 real data line 160 and the 7 real clock line on the 7 real clock line 161 when 8 bit data is continuously transferred to the processing device 130 will be explained. In this embodiment, the serial cross flag 105 on the first serial data processing device 100 is set;
The first 7 real data processing device 100 is a serial
On the other hand, the serial clock source flag 135 on the second serial data processing device 130 is cleared and the serial clock is input from the serial clock terminal 137. It is assumed that it is set to be a slave that performs transmission and reception. The serial clock line 161 maintains a high level during non-transfer. The data processing unit 103 is connected to the internal data bus 10
When the transmission data is transferred to the shift register 101 at the timing of two・ via 8, ACK detection 7 lag 11
5 is cleared at the same timing of <tlo・. Serial black, ri generation circuit] 02 is! 1 (H timing), the serial clock signal starts to be generated, and the serial clock signal is output via the terminal 107.

[Send this black and white data to serial black and white] 61. Shift register]0] is the falling edge of the 7 real clock generated from the clear control circuit 1]3.
Performs foot operation for 1 bit in synchronization with , and transfers 1 bit of the final stage of shift register
] from the serial data terminal 106 to the real data line 160 via the real data line 160. Continuing, the shift register 10] is a serial clock, a rising edge, and a tl
・3. tl・S. t1@t e'! III t fullll * FIS
The shift operation is repeated in synchronization with each timing of -fill, and the bits are sent from the serial data terminal 106 to the serial data line 160 in the order of the bits stored in the final stage of the shift register 10. When the sending of 7 real data of ',) (1 byte) is completed at the timing of 111m, the ACK detection circuit 104 detects the next falling edge ttt.
The line driver 110 is set to high level at timing y. At the same timing of t1!7, the serial clock control circuit 13 outputs an ACK sang signal 117. The serial clock generation circuit 102 generates a clear clock regardless of this. ri continues to occur. The ACK detection circuit 104 is a riser,
Ji t18. In synchronization with the timing of , the serial data rhino 160 is Sangli-nobbed to start detecting a low-level signal sent from the second serial data processing device 130 as a reception confirmation signal. The second serial data processing device 130 has 7 real clocks,
Clyno 161 also has serial clock, serial clock input via terminal 137, riser, and t1/3.
The first one on serial data line 160
Bit and bit data are shifted into the shift register 131 via the serial data terminal 136. Continue, 'l
・4. tl... weight1@l * t11@ * '11m -F14 e
Seventy-seven bits of data input via the serial data line 160 are sequentially input to the shift register 131 in synchronization with the timing of t11@. At the timing of shift black, ri no riser, and ji tll-, 8 bit, g (1
When the reception of the 8-bit serial data (byte) is completed, the data processing unit 133 reads out the 8-bit data input to the shift register 131 onto the internal data bus 38. The 7 real clock control circuit 143 inputs the reception end signal 150 to the ACK output circuit 144 at the timing t11@ of receiving the 8th bit serial data. Since the ACK output selection flag 146 is @1m, when the reception end signal 150 is manually input, it has no relation to other signals (the ACK output circuit 144 is sent to the first 7 real data processing device on the transmitting side) 00. As a reception confirmation signal, the next falling quagge t
Ill? At this timing, a low level signal is output from the clear data terminal 136 to the 7 real data rhino 160 via the ACK output driver 142. The ACK detection circuit 104 of the first 7 real data processing device 100 performs a serial clock start-up process. Serial data rhino 1 at the timing of 1118
60 and detects a low level signal sent as a reception confirmation signal from the second serial data processing device 130, the ACK detection flag 115 is set. The serial clock control circuit 113 controls the next riser and tax. Serial clock output is stopped at the timing of . The data processing section 103 is the ACK detection circuit 10
4 through the internal data bus 108, the second serial data processing device 130 determines that all processing in data reception has been completed, and transfers 1 byte of serial Finish the data transmission process. The data processing unit 103 then transfers the next transmission data to the shift register 16 and starts the transmission process of the next 7 real data. The serial data line 160 when 8 bits of data are continuously transferred from the second serial data processing device 130 to the first serial data processing device 100 when the ACK output selection flag 116 is @1”.
The synchronization relationship between the above serial data and the serial data and the 7 real clocks on 61 is the same as the synchronization relationship during transfer from the first serial data processing device 100 to the second serial data processing device 30. Since they are the same, detailed explanation will be omitted here. Next, referring to FIG. 6, when the ACK output selection flag 146 is 10# and it is necessary to perform error checking, data processing, etc. after data reception, the second serial Data processing device] 30
The synchronization relationship between the serial data and serial data on the Rhino 60 and the 7 real black and ri on the Cryno 161 when continuously transferring 0-bit and tono data to the Rhino 161 will be explained. The first 7 real data processing device 100 is the master, the second
7. The real data processing device 130 is assumed to be a slave. [Data processing unit] 03 transfers the transmission data to the shift register 1 via the internal data bus 108 at the timing of ts...
When transferred to 01, the ACK detection flag 1]5 is the same ts.
・It will be cleared at the timing of. The serial clock generation circuit 102 starts generating serial clocks and clocks at the timing t set , and the clocks and clocks are sent from the serial clock terminal 107 to the 7 real clock line 161 . The shift register 101 is a clear control circuit that performs a shift operation for 1 bit in synchronization with the falling edge of the serial clock generated from 3, The data is sent from the clear data terminal 106 to the serial data line 160 via the pit line driver 110. Continuing, 7 foot register 101 digit 7 real black, 1 falling edge of ts・3・t sos・ts・1・
The shift operation is repeated in synchronization with each timing of tme, tsxt, tN1@@tlll, and when the shift register 7 is shifted to the final stage of shift register 01, it is sequentially sent to 7 real data rhino 60. 7 When all 8 bits of serial data have been sent at the timing of the falling edge of the real clock, bit Ill, the ACK detection circuit 104 detects the next falling edge of the real clock, bit 1.
1? Line driver 1]0 is set to high level at the timing of . At the same timing of tsly, the control circuit 113 outputs an ACK signal 11.
Outputs 7. The serial clock generation circuit 102 continues to generate serial clock signals and the ACK detection circuit 10.
4 stands up, ji' 818 * tsta...
・In synchronization with each timing, serial data line 1
The second serial data processing bag [detects the low level signal sent from 130 as a reception confirmation signal ◇ Second 7 real data processing device] 30 is a serial clock Serial clock input from line 161, 7 real clock input via terminal 137, start-up time, dits
In synchronization with OW, the first 1-bit data from the serial data line 160 is shifted into the 7-ft register 131 via the serial data terminal 136. Continue s ts・4゜t3＠＠ e '＄＠I * tst
In synchronization with each timing of e I tsta I tsta so tsts, 77 pieces of data of each subsequent bit are sequentially input to the shift register 13. When the reception of 8 bits (1 byte) of serial data is completed at the timing of 7 feet, 7 feet, and 7 feet register 131, the data processing unit 133
The 8-bit data input to the internal data bus 138
and perform the necessary processing. The serial clock control circuit 143 sets the reception confirmation signal 150 to "]" at timing t31 when receiving the 8th bit of 7 real data, and inputs the error to the ACK output circuit 44. At this time, the ACK output selection flag]46 is 1
Since it is 0#, no reception confirmation signal is output. When the data processing section 133 finishes the necessary processing on the received data at timing t4..., it outputs an ACK write signal 49 to the ACK output circuit 46. Synchronize with this signal 149

The end signal “1” output from the data processing unit 133 is input to the ACK output circuit 44 via the internal data bus 138 and the signal line 151. A
The CK output circuit 144 outputs an ACK output driver 1 at the timing of the next falling edge, t4·l, as a reception confirmation signal to the first 7 real data processing device 100 on the transmitting side.
42, a low level signal is output from the clear data i child 136 to the 7 real data line 160. The ACK detection circuit 104 in the first serial data processing device 100 causes the 7 real data line 160 to go to low level at the timing of the rising edge of the serial clock, t4. When it is confirmed that 130 has output a reception confirmation signal, the ACK detection flag 1]5 is set. Serial clock control circuit 1] 3
stops outputting the serial clock at the timing of the next rising edge, t464. When the data processing unit 103 confirms that the ACK detection flag 115 is set, the second 7 real data processing unit 30 determines that all processing in data reception has been completed, and transmits 1 byte of serial data. Finish the process. After the transfer, the data processing unit 103 can resume the transmission of the next 7 real data by setting the next transmission data in the 77 register 10]. First 7 Real Data Processing System fi! :100 manages the time until the reception confirmation signal is returned, so that the second 7 real data processing can be performed even after the period of T] after the reception confirmation signal is ACKed/Grinnob signal 117 is set. If the data is not output from the device 130, it is assumed that an abnormal situation has occurred in the second serial data processing device 30, and the transmission of the real data from the first serial data processing device 100 can be stopped. When the ACK output selection flag 116 is 10'', the serial data on the serial data line 160 is The synchronization relationship between the serial chronograph, the 7real chronograph on the Cryno 161, and the 7real chronograph on the Cryno 161 is the same as the synchronous relationship during transfer from the first 7real data processing device 100 to the second serial data processing device 130. A detailed explanation will be omitted here. [Embodiment 2] A second embodiment of the present invention will be explained with reference to FIG. , ri generation circuit 102, data processing section 103. Serial clock, cross flag 105. Serial data terminal 106.7 Real clock, ri terminal 107
．． Internal data bus 108, line buffer 109. Line driver 110.7 Real black control circuit 113.
ACK detection circuit 104. ACK output circuit 114. Black. driver 111. and an ACK output driver 112. Among these, the functions other than the ACK output circuit 114 are the same as those shown in the first embodiment, so detailed explanations will be omitted here. The ACK output circuit 114 has an ACK output selection flag]16
and serial black, including Kukaunota 125. The serial clock counter 125 will be explained using FIG. Serial Kuro, Kukaunota] 25 is a subtractor] 2
7 and count register ] 26. The count register 126 receives internal data bus 1 from the data processing unit 103.
08, timing information n for outputting an input reception confirmation signal is stored in synchronization with the control signal 128. The subtracter 127 is a serial clock. When the generation of the error starts, the kakunt number n stored in the count register 126 is set to 7 real clocks. In synchronization with the downhill slope, the slope is decremented by 11m. When a borrow occurs, A in the ACK output circuit 114
Outputs 11' to the CK generation circuit and outputs ACK output driver 1.
A lower level signal as a reception confirmation signal is output from the serial data terminal 06 to the serial data rhino 160 via the serial data terminal 12. The ACK output selection flag 116 is the first
Similar to the example, @
Set to 0" or 11". The configuration and functions of the second 7 real data processing device 130 are the same as those of the first serial data processing device [00], so a detailed explanation will be omitted here. Next, referring to FIG. 3, the operation when 8 bits (1 byte) of data is continuously transferred from the first V real data processing device 100 to the second serial data processing device 130 will be explained. do. When the ACK output selection flag is set to 10" by software processing, the same processing as in the first embodiment is performed, so a detailed explanation will be omitted.
If 6 is set to 11”, the force 9 register is set to 156.
The timing for outputting the reception confirmation signal can be arbitrarily selected such as the 8th shot, the 9th shot, the 10th shot, etc. according to the set value in the above. For example, if the processing of received data is t
If you finish by the l/tatami timing, 10 shots 0
Count register 156 so that a reception confirmation signal can be issued to
The first serial data processing device 100 should be set to 19" in advance. The first serial data processing device 100 has 7 real black, 19", and 19" as in the first embodiment.
'? e3 e ties I @t@t
@ @10 @ e htt -t713 *
Data is sent to the serial data rhino 160 in synchronization with each timing of tma1$. [Second 7 Real Data Processing Device] 30 is a serial clock input from the cryograph 161 through the serial clock terminal 137, and the rising edge t1 of the serial clock input through the terminal 137.
Snow・t 714・t? I...tl・lu・ht...t 7
1m/t? 14.t? In synchronization with each timing of number 1,
Serial data from the 7 real data line 160 is sequentially shifted into the shift register 131. 7 real black, ri no riser, ji t, 8 at 1°0 timing, and when the reception of 7 real data of g is completed, data processing unit 1
33 reads out the 8-bit data in the shift register 131 to the internal chip')Ax138. Further, at the timing of the first serial clock, the value of the count register 156 in the serial clock counter 155 is set in the subtracter 157. Now, if 19 m is set in the subtractor 157, it is the first downhill. It is decremented by 111 at the timing of t1゜l and becomes 1.
8".Subsequently, the value of the subtracter 157 is decremented by "1" at each timing of the falling edge and ji, and a borrow occurs at the timing of t,.1. As a result, the value of the subtracter 57 to 111 A reception confirmation signal is output from the ACK output circuit 144 in synchronization with the same timing t8·1.'As described above, the 7 real data processing device of the second embodiment has a reception confirmation signal output timing. can be set arbitrarily, so there is an advantage that the time for processing the received data can be changed as appropriate.
There is also the advantage that software 9 air processing required to notify the K output circuit 144 of the end of data processing is unnecessary. Note that a predetermined value may be set to the subtracter by hardware. FIG. 4 is a circuit block diagram of the 7-real black, Kukakunota, and their surroundings in the second 7-real data processing device [30], which is exactly the same as that in FIG. 3. [Effects of the Invention] As explained above, the serial data processing device based on the present invention returns a reception confirmation signal from the ACK output circuit to the transmitting side after completing the processing of received data, so that it is possible to notify the transmitting side of the completion of reception. It has the effect of being able to. Furthermore, when an abnormal situation occurs on the receiving side, there is the effect that reception rejection can be notified by prohibiting the transmission of a reception confirmation signal to the transmitting side within a certain period of time. Furthermore, since it has an ACK output selection flag, depending on the received data, the output of the reception confirmation signal is synchronized when 8-bit serial data is received, or when the necessary processing of the received data in the data processing section is completed. You can select when to synchronize using software 9 air. Since continuous high-speed 7-real data transfer of multiple bytes eliminates the need for software processing to notify the end of data processing, it is possible to significantly improve the processing efficiency of the CPU. Note that it is clear that the present invention can be applied to high-speed serial transfer (DMA transfer) that does not involve a data processing section.

[Brief explanation of the drawing]

Figure 1 is a system configuration diagram of the first embodiment of the present invention;
The figure is a system configuration diagram of the second embodiment of the present invention, FIG.
Fig. 4 is a diagram of the serial clock, Kukaunota, and its surroundings in the second embodiment, Fig. 5 is a timing chart when the ACK output selection flag is 11'', and Fig. 6 is a timing chart when the ACK selection flag is 10''. ”, FIG. 7 is a timing chart in the second embodiment,
FIG. 8 is a reference diagram of the present invention, and FIG. 9 is a timing chart thereof. 100.400...First 7 real data processing device, 130.420...Second 7 real data processing device, 101,131,401.421...
・7 register, 102,132,402.422
・・・・・・Serial black, ri generation circuit, 103, 13
3゜403.423...Data processing section, 104
, 134...ACK detection circuit, 105, 135
,405゜425... Serial black, Kutosu flag, 106゜136.406,426...
Serial data terminal, 107.137, 407, 427
・・・・・・Serial black, terminal, 108, 138,
408, 428... Internal data bus, 109.
] 39,409°429...Lights bar, Fa, 110,140°410.430...Line driver, 111°14], 411.431...
・Black, Kudriver, 112.142...AC
K output driver, 113°143... Serial clock control circuit, 114°144...ACK
Output circuit, 115.145...ACK detection flag, 116,146...ACK output selection flag, 117.147...ACK sensor signal, 1
19.149...ACK light signal, 120.1
50...8 bit, received signal, 121°15]・
...Data processing end signal, 122.152...
...Reception confirmation signal, 125,155... Serial black, Kukau/ri, 160.440... Clear data rhino, 161,441...7 Real black. Klein, 126.156...Count register, 127.157...Subtractor, 128.15
8...Control signal.ゝ・（こ： ′

Claims (1)

[Claims] In a serial data processing device connected to a single data line and a single clock line, an output circuit outputs a reception confirmation signal on the data line and generates a first signal indicating completion of reception of serial data. a circuit that generates a second signal to notify that processing of the received data is completed; and a circuit that controls output of the reception confirmation signal, and the reception of the serial data on the data line is completed. Then, the output circuit outputs the reception confirmation signal to the data line in synchronization with the first signal or the second signal.