JPS6365223U - - Google Patents
Info
- Publication number
- JPS6365223U JPS6365223U JP1986159750U JP15975086U JPS6365223U JP S6365223 U JPS6365223 U JP S6365223U JP 1986159750 U JP1986159750 U JP 1986159750U JP 15975086 U JP15975086 U JP 15975086U JP S6365223 U JPS6365223 U JP S6365223U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- substrate
- melting point
- point metal
- alignment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002844 melting Methods 0.000 claims 3
- 239000002184 metal Substances 0.000 claims 3
- 239000000758 substrate Substances 0.000 claims 3
- 230000008018 melting Effects 0.000 claims 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986159750U JPS6365223U (US07655688-20100202-C00086.png) | 1986-10-17 | 1986-10-17 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986159750U JPS6365223U (US07655688-20100202-C00086.png) | 1986-10-17 | 1986-10-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6365223U true JPS6365223U (US07655688-20100202-C00086.png) | 1988-04-30 |
Family
ID=31084476
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986159750U Pending JPS6365223U (US07655688-20100202-C00086.png) | 1986-10-17 | 1986-10-17 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6365223U (US07655688-20100202-C00086.png) |
-
1986
- 1986-10-17 JP JP1986159750U patent/JPS6365223U/ja active Pending