JPS6342458B2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to a diversity communication method used to improve transmission characteristics in digital mobile communications where bit error rate characteristics are significantly degraded due to multipath fading, etc. be.

(Background Art) Diversity communication methods in conventional digital mobile communications include) selection diversity,
) antenna switching diversity, ) time diversity, etc. ) selection diversity uses multiple antennas and receivers and selects the receiver output that provides the highest reception level, but since the method requires multiple receivers, the improvement effect is excellent. However, it is expensive, and has drawbacks such as an increase in the size of the device. In addition, antenna switching diversity () uses multiple antennas and one receiver, and switches to another antenna when the reception level falls below a threshold level.It can be configured with one receiver and is compact. -Although it has the advantage of being economical, it has the fatal disadvantage of causing discontinuity in carrier wave amplitude and phase when switching antennas, which appears as large switching noise in the detection output, resulting in a significant deterioration of code error characteristics. Ta. ) time diversity does not have the above-mentioned drawbacks, but it uses the principle that the correlation between signals transmitted at delay time intervals is low, so as the fading speed becomes slower, the correlation between the diversity branches decreases. This has the disadvantage that the diversity effect disappears when the moving object becomes large and the moving object stops.

(Problems to be solved by the invention) In order to eliminate such drawbacks, the present invention uses code redundancy in time diversity to compensate for code errors caused by switching noise, which is a problem in antenna switching diversity, and also The antenna switching diversity is used to compensate for the decrease in the time diversity effect when the speed is small, and will be described in detail below with reference to the drawings.

(Structure and operation of the invention) FIG. 1 is an embodiment of a method for allocating time for transmitting and receiving signals in the diversity communication system of the present invention. For simplicity, a case will be described in which the number of interlaced transmissions is two and the number of diversity reception antennas is two.

The data sequence 1 of the signal to be transmitted, such as an encoded audio signal or facsimile signal, is {a _i } (i is an integer), the encoder output data sequence 2 actually sent from the transmitter is {b _i }, The received data series 5 is {c _i },
The decoded data series 6 output from the synthesis circuit is expressed as {d _i }. {a _i } is a data series of clock frequency _c , and when the number of interlaces is N, the clock frequency _c ′ of {b _i } must be set to N _c . In this example, it is twice, so _c ′=
2 _c . {a _i } is encoded into {b _i } in the following manner by an encoder in the transmitting device, which will be described later. In the odd time slot {b _2j+1 } of {b _i },
The data {a _i } input at that time is assigned as is. That is, b _2j+1 =a _i . On the other hand, {b _i }
The even time slots {b _2j } of are assigned n-bit delayed data {a _io } to be transmitted in an interlaced manner. That is, b _2j =a _io . The delay amount n bits is set to an arbitrary value equal to or more than about half a period of fading. In this way, {a _i } is interlaced and then sent out. When the above encoding is performed, as shown in the figure, _ao is assigned to the time slots of _b4o and b2o ₊₁ , and the time slots on both sides of b2o ₊₁ are
a ₀ and a ₁ are assigned to b _2o and b _2o+2 , respectively, and data without delay and data with delay are transmitted alternately.

On the receiving side, the reception level 3 is constantly monitored, and when the reception level crosses the threshold level (SL) from top to bottom, the antenna is switched. In FIG. 1, antenna 1 is switched to antenna 2. By this switching operation, the receiver can be connected to the antenna 2 with a high reception level, and the reception level distribution can be improved, so that the error rate characteristics are also improved. Antenna switching methods include:) switching only when the reception level crosses the threshold level from top to bottom (Switch &Stay); and) switching at regular intervals until the reception level exceeds the threshold level. (Switch & Examine),) A method of setting multiple threshold levels and comparing them with the reception level to perform switching (see Japanese Patent Application No. 1984-084793). However, when the antenna is switched, discontinuity occurs in the carrier wave amplitude and phase of the received signal, so switching noise appears in the detection output, resulting in a code error in the received data output. Conventionally, no effective method for removing this switching noise has been proposed, making it difficult to realize a system using an antenna switching method. Code errors due to switching noise occur in the area from immediately after switching to several bits later, and the amount varies depending on the modulation/demodulation method, reception bandwidth, etc. For example, signal speed 16kbps, switching frequency 40
Assuming that the number of code error bits per switching is 2 bits per second, the error rate will not be better than 5 x 10 ^-3 . In the present invention, a signal indicating the switching noise region immediately after switching is generated, and among N pieces of data repeatedly transmitted in an interlaced manner, the highest signal is selected from among the data from which the data falling within the switching noise region is removed. Time diversity reception is performed according to an algorithm that outputs data corresponding to the reception level, and the influence of switching noise is reduced. In the embodiment shown in Fig. 1, the 3 bits C _4o+4 to _{C 4o+6} are in the switching noise area, so these are removed.
Outputs C 2o ₊₅ to d 2o+ ₂ and outputs C _2o+7 to d _2o+3 .
In other areas, for example, C _2o+1 and C _4o , C _2o+3 and C _4o+2 , the data with higher reception level is d _2o ,
Output to d _2o+1 . As explained above, the present invention improves the reception level distribution by using the antenna switching method, removes switching noise by using time diversity, and performs selection diversity based on the reception level, and the synergistic effect of these can achieve a large code error rate improvement effect. This is what you get.

FIG. 2 is an example of a time allocation method. The encoding method in this embodiment will be explained below.

The encoder transmits 2 bits of transmitted data separated from each other by the number of bits (2n - 1) corresponding to a time interval that is equal to or longer than a half cycle of fading (n is an integer, and the reference clock is _c ).
One error detection bit is determined for each bit, and these three bits are set as one group, and the transmission data is output almost in real time, and the error detection bit is outputted at a time interval approximately equal to the above-mentioned time interval from the subsequent transmission data. By setting the time intervals in this way, the reception levels when each bit in the group is received are almost uncorrelated, so
In the demodulated data sequence, it is possible to reduce the probability that bits within a group will simultaneously cause code errors. Taking an example from FIG. 1, transmission data a ₁ becomes encoder output data b ₂ , a _2o becomes b _3o , code error detection bit a ₁ ○×a _2o becomes b _6o-2 (p _{4o- 2} ), and the interval between each bit is (3n-2) bits if _c ' is the reference clock. However, ○× means an operation to obtain a code error detection bit.
If we express this encoding in a formula, where k is an integer, b _3k = a _2k , b _3k+1 = p _2k = a _3k-6o+5 ○×a _3k-3o+3 , b _3k+2 = a _2k It can be expressed as ₊₁ . There are various methods for creating code error detection bits, such as parity and checksum, but as long as they are 1-bit error detection methods, the performance of the present invention is not affected by any of them. The above explanation is an example of adding one code error detection bit to every two bits of transmitted data, but in general, when N bits of transmitted data are grouped, the transmission efficiency is η=N/(N+1), which is better. Transmission efficiency improves.

On the receiving side, decoding is performed according to the following algorithm.

If the bits in the group are not within the switching noise region, error detection is performed for each group. (1) If there is no error, the data bits are output as they are at intervals of (2n-1) bits.

(2) If an error is detected, compare the received levels and if the bit corresponding to the lowest level is (a) one of the data bits,
It is assumed that an error has occurred in that bit, and this is corrected.

(b) If it is an error detection bit, output the data bit as is, as in (1).

When one bit is within the switching noise region: (a) If it is an error detection bit, output the data bit as is.

(b) If it is a data bit, generate it from other bits in the group and interpolate it.

When 2 bits or more are within the switching noise region,
Outputs data bits as is.

That is, this is an algorithm that performs 1-bit error correction using the redundancy of the error detection bit added to each group, and can eliminate code errors caused by switching noise and a drop in reception level.
In digital mobile communications, there is a close relationship between reception level and error rate, and as the reception level decreases, the error rate deteriorates rapidly. Therefore, if a method is used in which it is assumed that an error has occurred in the bit with the lowest reception level and this is corrected, there is almost no risk of error correction, and as mentioned above, the probability that bits within a group will have simultaneous errors can be reduced. Since the encoding is performed to suppress the error to a low level, it is possible to obtain a decoded data output in which most of the errors contained in the demodulated data are correctly corrected. Furthermore, the case like ) in the above algorithm occurs only when the antenna switching period matches the delay time interval of (3n-2) bits, and the probability of occurrence is quite low and does not pose a problem.

FIG. 3 shows an embodiment of a transmitting/receiving system in the diversity communication system of the present invention. The transmission data input from the terminal 9 is encoded by the encoder 10 as described above, and then applied to the modulator 11 together with the carrier signal output from the carrier wave generator 13.
The signal is modulated by the power amplifier 12 to the required transmission power, and then transmitted from the transmission antenna 14. After one of the radio waves received by the diversity receiving antennas 15 and 16 is selected by the antenna switch 17, it is detected by the receiver 18, the received data string is sent to the decoder 14, and the received level signal is sent to the control circuit 20.
is input. The control circuit outputs an antenna selection signal to the antenna switcher and a decoding control signal to the decoder according to the above-described switching algorithm and decoding algorithm based on the reception level. A decoded data sequence is obtained at the output terminal 21. Here, the diversity receiving antenna may be an antenna based on any diversity branch configuration method such as spatial diversity, polarization diversity, or directional diversity, and the number of antennas may be 2 or more. Also good.

FIG. 4 is a block diagram of an example of the configuration of encoder 10 in the embodiment of the present invention shown in FIG. The transmission data input from the input terminal 30 is (N-1)
The signal is applied through n-bit shift registers 33 to 35 to a gate circuit 36 having N input terminals. The shift register is the transmission clock (frequency _c )
is shifted. The gate circuit sequentially switches N inputs based on a high-speed clock with a frequency of N _c ,
It is output to terminal 37 as encoder output data. The clock generating circuit 32 generates two clock signals of frequencies _c and N _c and outputs them to the shift register, the transmission clock output terminal 31 and the gate circuit 36. An N-times interlaced signal is obtained from this encoder.

FIG. 5 is a block diagram of one configuration example of the encoder 10. The transmission data inputted from the input terminal 30 is applied to the error detection bit generator 38 indicated by the ○× marks along with the outputs through (N-1) pieces of (2n-1) bit shift registers 33 to 35. , _c '=(1+1/N) _c is input to the gate circuit 36 together with the error detection bit delayed by the (3n-2) bit shift register 39 operated by the clock. Out of the (N+1) input terminals, the gate circuit inputs the transmission data to N and the error detection bit to one, and switches the input sequentially at the clock frequency _c ', and outputs the encoder output data to the terminal 28. Output. The clock generation circuit 32 has a frequency
Two clock signals _c and _c ' are generated and output to the shift register, transmission clock output terminal 31, and gate circuit. From this encoder, the transmitted data N
Encoder output data with a transmission efficiency of N/(N+1) with one error detection bit added per bit is obtained.

FIG. 6 is a block diagram showing an example of the structure of the decoder 19 and control circuit 20 in the embodiment of the invention shown in FIG. The transmission level signal inputted from the input terminal 52 is outputted through a delay circuit 67, and after passing through gate circuits 64 and 65, respectively, is applied to a level comparison circuit 63 as a reception level signal corresponding to each bit of the interlaced signal. The signal is applied to the synthesizer 62 as a signal instructing it to select the higher level bit. The reception level signal is compared with the output level of the threshold generation circuit 70 in the level comparison circuit 69, and when it becomes lower than the output level, an antenna switching signal is applied to the antenna selection signal generation circuit 71, and the antenna selection signal output terminal 55 is applied to other reception signals. A switch to the antenna occurs. At this time, the synthesis prohibition timing generation circuit 72 outputs a timing signal for prohibiting the use of data between several bits immediately after switching, and applies it to the gate circuits 64 and 65 together with the timing signal delayed by the shift register 73. At the synthesis inhibit timing, the gate circuit operates by suppressing its level output to the lowest level so that data corresponding to this level will not be selected. On the other hand, received data is input from a terminal 51 and is applied to a combination detection circuit 59 and a combiner 62 through an n-bit shift register 56.
The combination detection circuit detects the correct combination of time slots and outputs this timing to the decoding clock generation circuit 60, which uses it as the frequency division reset timing of the reproduced clock, thereby obtaining the decoding clock. The synthesizer 62 takes out the data with the higher reception level at the decoding clock timing and outputs it to the terminal 54 as decoded data.

FIG. 7 is a block diagram showing an example of the configuration of the decoder 19 and the control circuit 20. The configuration is almost the same as that shown in FIG. 6, except that the operating algorithm of the synthesizer 62 is the same as that described in the explanation for FIG. Below, only the different points will be explained. If there is one more delay circuit and shift register each for the reception level signal, reception data series, and synthesis prohibition timing signal, and if one or more bits in the group are within the synthesis prohibition timing, the error detection circuit 61
There is an OR circuit for instructing the synthesizer 62 to output a signal indicating that an error has been detected;
The difference is that the circuit for instructing the decoding clock timing has been changed from the combination detection circuit to the error detection circuit 61.

(Effects of the Invention) As explained above, the diversity communication system of the present invention uses the code redundancy of time diversity to interpolate and remove code errors caused by switching noise that occurs when switching antennas, and also uses low-speed Since this is a diversity communication system that compensates for the decrease in time diversity effect during movement by using an antenna switching system, it is possible to reduce the degradation of the code error rate due to switching noise and the decrease in diversity effect due to a decrease in movement speed. The antenna switching method and the time diversity method have diversity effects obtained in different dimensions, so they are not easily affected by deterioration factors such as The number of is the product value of the number of each branch, and the diversity effect can be increased more efficiently than increasing the number of branches using only one method. It is suitable for miniaturization and economy, which are essential conditions for communication, and although the control circuit is somewhat complex, most of it is a digital circuit, making it suitable for LSI implementation.
It is easy to replace with software control by a microcomputer, and a transmission system with a large diversity effect as described above can be realized with a simple configuration, so it can be used not only for voice communication but also for image communication such as facsimile, etc. Even for communications that require extremely high-quality transmission paths, such as data communications, there are advantages such as the ability to easily achieve this by setting the number of antennas and the number of signal interlaces to values that provide the required quality. be.

[Brief explanation of the drawing]

1 and 2 are diagrams showing an example of the time allocation configuration of transmitting and receiving data sequences, FIG. 3 is a block diagram showing the configuration of an embodiment of a transmitting and receiving device in the diversity communication system according to the present invention, and FIGS. FIG. 5 is a block diagram showing an example of the configuration of the encoder, and FIGS. 6 and 7 are block diagrams showing examples of the configuration of the decoder and control circuit. 1... Transmission data series, 2... Encoder output data series, 3... Reception level signal, 4... Antenna selection signal, 5... Reception data series, 6... Decoded data series,
DESCRIPTION OF SYMBOLS 10... Transmission device, 11... Receiving device, 12... Transmission data input terminal, 13... Encoder, 14... Modulator, 1
5... Power amplifier, 16... Carrier wave generator, 17... Transmitting antenna, 18-19... Diversity receiving antenna, 20... Antenna switching device, 21... Receiver,
22...Decoder, 23...Control circuit, 24...Decoded data output terminal, 30...Transmission data input terminal, 31...
Transmission clock output terminal, 32...Clock generation circuit, 33-35...Shift register, 36...Gate circuit, 37...Encoder output terminal, 38...Error detection bit generator, 39...Shift register, 50...Regeneration clock input terminal, 51... Reception data input terminal,
52...Reception level input terminal, 53...Decoded clock output terminal, 54...Decoded data output terminal, 55...Antenna selection signal output terminal, 56-57...Shift register, 59...Combination detection circuit, 60...Decoded clock generation circuit, 61 ...Error detection circuit, 62...Synthesizer, 63...Level comparator, 64-66...Gate circuit, 67-68...Delay circuit, 69...Level comparison circuit, 70...Threshold value generation circuit, 71...Antenna selection signal generation Circuit, 72... Synthesis inhibition timing generation circuit, 73-74... Shift register.

Claims (1)

[Claims] 1. In digital mobile communications, the transmitting side is equipped with encoding means for converting transmitted data into an interlaced signal that is repeated twice or more at a time interval equal to or longer than a half period of fading. However, on the receiving side, there is provided a diversity receiving antenna consisting of a plurality of antennas, an antenna switching means for switching between the diversity receiving antennas, and a switching means for switching the antenna to another antenna when the reception level crosses a threshold level from top to bottom. switching control means for instructing the antenna switching means to switch; and after removing received data affected by switching noise accompanying antenna switching, each interlaced received signal appears on a plurality of diversity branches. It is equipped with a decoding means that selects and combines the received data according to the reception level of each received signal, eliminates received data that has code errors caused by switching noise, and replaces it with data that has been transmitted and received at other times. A diversity communication method characterized by reducing deterioration of the diversity effect due to switching noise by interpolating this with data. 2. As a switching control means, when the reception level is below the threshold level, the antenna is configured to switch the diversity receiving antennas one after another at intervals of the time required to detect the reception level until the reception level exceeds the threshold level. The diversity communication system according to claim 1, characterized in that switching control means is used to give instructions to the switching means. 3. As a switching control means, a plurality of threshold values are provided, and when the reception level falls below the threshold level set at that time, an instruction is given to the antenna switching means to switch the antenna, and after switching, a threshold value is set. If you change the value to a lower threshold and the reception level exceeds the threshold that is higher than the currently set threshold,
Like changing the threshold to a higher threshold.
2. The diversity communication system according to claim 1, characterized in that a switching control means is used to automatically control antenna switching and threshold change according to a reception level. 4 In digital mobile communications, on the transmitting side,
Equipped with encoding means for adding a 1-bit error detection code to two or more bits of transmitted data separated by a time interval equal to or longer than a half cycle of fading, and on the receiving side, a plurality of a diversity receiving antenna consisting of an antenna;
antenna switching means for switching the diversity receiving antenna; switching control means for instructing the antenna switching means to switch the antenna to another antenna when the reception level crosses a threshold level from top to bottom; Receive data affected by switching noise due to antenna switching is removed, and this is interpolated using error detection bits.
Error detection is always performed on received data that is not affected by switching noise, and when an error is detected, it is assumed that an error has occurred in the data corresponding to the lowest reception level, and a decoding means that corrects the error is provided. 1. A diversity communication system comprising: interpolating data in which code errors have occurred due to switching noise using error detection bits to reduce deterioration of diversity effect due to switching noise. 5. As a switching control means, when the reception level is below the threshold level, the diversity reception antennas are switched one after another at intervals of the time required to detect the reception level until the reception level exceeds the threshold level. 5. The diversity communication system according to claim 4, characterized in that switching control means for giving instructions to antenna switching means is used. 6 As a switching control means, a plurality of threshold values are provided, and when the reception level falls below the threshold level set at that time, an instruction is given to the antenna switching means to switch the antenna, and after switching, If you change the threshold to a lower threshold and the reception level exceeds the threshold that is higher than the currently set threshold,
Like changing the threshold to a higher threshold.
5. The diversity communication system according to claim 4, characterized in that switching control means is used to automatically control antenna switching and threshold change depending on the reception level.