JPS6340410A - Signal control circuit - Google Patents

Signal control circuit

Info

Publication number
JPS6340410A
JPS6340410A JP61185559A JP18555986A JPS6340410A JP S6340410 A JPS6340410 A JP S6340410A JP 61185559 A JP61185559 A JP 61185559A JP 18555986 A JP18555986 A JP 18555986A JP S6340410 A JPS6340410 A JP S6340410A
Authority
JP
Japan
Prior art keywords
signal
gate
turned
condition
transfer gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61185559A
Other languages
Japanese (ja)
Inventor
Masaaki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP61185559A priority Critical patent/JPS6340410A/en
Publication of JPS6340410A publication Critical patent/JPS6340410A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To avoid the simultaneous change of a signal and to prevent a malfunction by forming a signal control circuit by an inverter gate, an exclusive OR gate and a buffer gate and prohibiting that all other signals are changed when one signal is in a changing condition.
CONSTITUTION: A latch circuit is constituted of transfer gates 6 and 7, inverter gates 4 and 5, and buffer gates 1∼3 and an input transition detecting circuit is constituted of an exclusive OR circuit 8. When a control signal 101 from an input terminal CI is 1, the transfer gate 6 is turned off and the transfer gate 7 is turned on and a latch circuit comes to be a latching condition. Reversely, when the control signal 101 from the terminal CI is 0, the transfer gate 6 is turned on, the transfer gate 7 is turned off and the latch circuit comes to be a data through condition. When a data signal 104 from an input terminal DI is in the transition condition, an input transition condition detecting signal 108 is generated from an output terminal CO.
COPYRIGHT: (C)1988,JPO&Japio
JP61185559A 1986-08-06 1986-08-06 Signal control circuit Pending JPS6340410A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61185559A JPS6340410A (en) 1986-08-06 1986-08-06 Signal control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61185559A JPS6340410A (en) 1986-08-06 1986-08-06 Signal control circuit

Publications (1)

Publication Number Publication Date
JPS6340410A true JPS6340410A (en) 1988-02-20

Family

ID=16172927

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61185559A Pending JPS6340410A (en) 1986-08-06 1986-08-06 Signal control circuit

Country Status (1)

Country Link
JP (1) JPS6340410A (en)

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