JPS6340355A - Three-dimensional semiconductor integrated circuit - Google Patents

Three-dimensional semiconductor integrated circuit

Info

Publication number
JPS6340355A
JPS6340355A JP61184419A JP18441986A JPS6340355A JP S6340355 A JPS6340355 A JP S6340355A JP 61184419 A JP61184419 A JP 61184419A JP 18441986 A JP18441986 A JP 18441986A JP S6340355 A JPS6340355 A JP S6340355A
Authority
JP
Japan
Prior art keywords
clock
response
semiconductor layer
logic circuits
actuating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61184419A
Other languages
Japanese (ja)
Inventor
Sumitaka Takeuchi
Masahiko Yoshimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61184419A priority Critical patent/JPS6340355A/en
Publication of JPS6340355A publication Critical patent/JPS6340355A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout

Abstract

PURPOSE:To highly integrate logic circuits acutuated by n-phase clock by a method wherein logic circuits actuating in response to the same clock are formed into an n-phase laminated structure on the same semiconductor layer. CONSTITUTION:Logic circuits 1, 4 actuating in response to a clock 1 are formed on the same semiconductor layer 100. Another logic circuit 2 actuating in response to another clock 2 i.e. with data transfer timing controlled is formed on another semiconductor layer 200. The other logic circuit 3 transferring data in response to the other clock 3 is formed on the other semiconductor layer 300. Thus, the capacitance formed between clock signal lines 9, 10, 11 and a data signal line is decreased to narrow the wiring region. Through these procedures, the logic circuits actuated by n-phase clock can be highly integrated.
JP61184419A 1986-08-05 1986-08-05 Three-dimensional semiconductor integrated circuit Pending JPS6340355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61184419A JPS6340355A (en) 1986-08-05 1986-08-05 Three-dimensional semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61184419A JPS6340355A (en) 1986-08-05 1986-08-05 Three-dimensional semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6340355A true JPS6340355A (en) 1988-02-20

Family

ID=16152833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61184419A Pending JPS6340355A (en) 1986-08-05 1986-08-05 Three-dimensional semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6340355A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH055462U (en) * 1991-07-05 1993-01-26 沖電気工業株式会社 Optical writing head for electrophotography
JP2012164794A (en) * 2011-02-07 2012-08-30 Sony Corp Laminate wiring board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH055462U (en) * 1991-07-05 1993-01-26 沖電気工業株式会社 Optical writing head for electrophotography
JP2012164794A (en) * 2011-02-07 2012-08-30 Sony Corp Laminate wiring board

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