JPS6335129B2 - - Google Patents
Info
- Publication number
- JPS6335129B2 JPS6335129B2 JP9020280A JP9020280A JPS6335129B2 JP S6335129 B2 JPS6335129 B2 JP S6335129B2 JP 9020280 A JP9020280 A JP 9020280A JP 9020280 A JP9020280 A JP 9020280A JP S6335129 B2 JPS6335129 B2 JP S6335129B2
- Authority
- JP
- Japan
- Prior art keywords
- row
- memory cells
- tristable
- column
- same
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 210000004027 cell Anatomy 0.000 claims description 73
- 210000000352 storage cell Anatomy 0.000 claims description 29
- 239000011159 matrix material Substances 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 16
- 229920000747 poly(lactic acid) Polymers 0.000 description 11
- 230000006870 function Effects 0.000 description 9
- 230000010354 integration Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Read Only Memory (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9020280A JPS5715533A (en) | 1980-07-02 | 1980-07-02 | Logical array circuit possible for write-in |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9020280A JPS5715533A (en) | 1980-07-02 | 1980-07-02 | Logical array circuit possible for write-in |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5715533A JPS5715533A (en) | 1982-01-26 |
JPS6335129B2 true JPS6335129B2 (enrdf_load_stackoverflow) | 1988-07-13 |
Family
ID=13991895
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9020280A Granted JPS5715533A (en) | 1980-07-02 | 1980-07-02 | Logical array circuit possible for write-in |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5715533A (enrdf_load_stackoverflow) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04502679A (ja) * | 1989-10-23 | 1992-05-14 | マイクロソフト コーポレイション | キーボードに取り付け可能な調節自在のクランプを備えたポインティングデバイス |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4774421A (en) * | 1984-05-03 | 1988-09-27 | Altera Corporation | Programmable logic array device using EPROM technology |
-
1980
- 1980-07-02 JP JP9020280A patent/JPS5715533A/ja active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04502679A (ja) * | 1989-10-23 | 1992-05-14 | マイクロソフト コーポレイション | キーボードに取り付け可能な調節自在のクランプを備えたポインティングデバイス |
Also Published As
Publication number | Publication date |
---|---|
JPS5715533A (en) | 1982-01-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10756738B2 (en) | JTL-based superconducting logic arrays and FPGAS | |
EP0081917B1 (en) | Programmable multiplexer | |
US5125098A (en) | Finite state-machine employing a content-addressable memory | |
US4034356A (en) | Reconfigurable logic array | |
US6876228B2 (en) | Field programmable gate array | |
US5654650A (en) | High throughput FPGA control interface | |
US4847612A (en) | Programmable logic device | |
KR100235812B1 (ko) | 시프트 레지스터 및 프로그래머블 논리회로 및 프로그래머블 논리회로시스템 | |
US20110167241A1 (en) | Superconducting circuit for high-speed lookup table | |
US6865639B2 (en) | Scalable self-routing superconductor switch | |
US5250859A (en) | Low power multifunction logic array | |
US20020057621A1 (en) | Programmable logic array device with random access memory configurable as product terms | |
US3761902A (en) | Functional memory using multi-state associative cells | |
US5924115A (en) | Hierarchical memory architecture for a programmable integrated circuit having an interconnect structure connected in a tree configuration | |
JPH03166625A (ja) | プログラマブル論理素子のための論理ブロック | |
US4327424A (en) | Read-only storage using enhancement-mode, depletion-mode or omitted gate field-effect transistors | |
US5467029A (en) | OR array architecture for a programmable logic device | |
US5349670A (en) | Integrated circuit programmable sequencing element apparatus | |
CN117271436B (zh) | 基于sram的电流镜互补存内计算宏电路、及芯片 | |
US4617653A (en) | Semiconductor memory device utilizing multi-stage decoding | |
US5742741A (en) | Reconfigurable neural network | |
US5369618A (en) | Serial access memory | |
US5003202A (en) | Coincidence extendable programmable logic device | |
EP0252654A2 (en) | Memory device with programmable output structures | |
JPS6335129B2 (enrdf_load_stackoverflow) |