JPS6335023A - Automatic equalizer - Google Patents

Abstract

PURPOSE:To decrease the transmission delay time by shifting all tap coefficients to the side remotest to the input end by one shift when a subtraction value is larger than a prescribed threshold value and shifting the coefficient to closest side to the input end by one stage when the subtraction value is smaller than another threshold value slightly smaller than the former threshold value. CONSTITUTION:An adder 21 subtracts an output CR of an adder 20 from an output CL of an adder 19 and gives the result to a decider 22. When the value is larger than a threshold value, the decider 22 supplies a shift pulse so as to shift right a shift register 2 by one stage, the tap coefficient of the most right end is lost as the result of shift and zero is inputted to a tap coefficient of the most left end. When an output of the adder 21 is smaller than another threshold value slightly smaller than the former threshold value, the decider 2 supplies a shift pulse so as to shift the shift register 2 to the left by one stage. As the result of shift, the tap coefficient of the most left end is lost and zero is inputted to the tap coefficient of the most right end. Thus, the delay time is decreased by one stage of tap.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic equalizer, and more particularly to an automatic equalizer with a delay time as short as possible.

[Conventional technology and its problems]

Conventionally, many studies have been made regarding automatic equalizers used in modulators and demodulators, but no study has yet focused on the delay time.

Modulation and demodulation equipment is originally used for data communication, but the amount of data that can be transmitted per unit time,
In other words, the so-called throughput depends not only on the data transmission rate of the modulator and demodulator but also on the transmission delay time incurred by the modulator and demodulator. Although this is well known, conventionally, when improving throughput, attention has tended to be focused only on the former, and the latter, the transmission delay time due to the modulation/demodulation device, has been apt to be ignored.

An object of the present invention is to improve throughput by reducing the transmission delay time of a modulation/demodulation device.
Particularly regarding an automatic equalizer that accounts for a major portion of the transmission delay time, it is an object of the present invention to provide an automatic equalizer with a delay time as short as possible.

[Means for solving problems]

The gist of the present invention is to calculate the sum of the squared values of the tap coefficients of several taps closest to the input end and the same number of taps farthest among the taps of the automatic equalization layer. , when the value obtained by subtracting the latter value from the former value is greater than a certain threshold value, all tap coefficients are shifted one stage to the side furthest from the input end, and another value slightly smaller than the threshold value is shifted. If it is smaller than the threshold value, the step is to shift one step to the nearest side.

Therefore, in an automatic equalizer having taps, the present invention provides a first means for calculating the sum of squares of tap coefficients of several taps closest to the input end among the taps of the automatic equalizer. , a second means for calculating the sum of the squares of the respective tap coefficients of the taps on the side closest to the input end and the same number of taps on the side furthest from the input end; and from the output value of the first means. comprising means for subtracting the output value of the second means and means for determining the magnitude of the subtracted value, and when the subtracted value is greater than a predetermined threshold, all the tap coefficients are set to the maximum value. Shift one step to the side farthest from the input end,
When the value is smaller than another threshold value that is slightly smaller than the threshold value, the signal is shifted by one stage to the side closest to the input end.

[Effect]

The delay time incurred by the automatic equalizer is equal to that of the tap with the largest tap coefficient, the so-called center tap.
Determined by the position from the tap on the side closest to the input end (this is defined as the left side).

From the perspective of shortening the delay time, it is preferable for the center tap to be located further to the left, but if it is moved too far to the left, some of the ideal tap coefficients determined by the characteristics of the transmission path will be forced to the left. This results in an increase in the equivalent residual error power.

When the tap coefficient of a certain tap is forcibly set to zero, the amount of increase in the equivalent residual error power due to this operation is equal to the value of that tap coefficient, assuming that the original tap coefficient matches the ideal value. It is clear from the superposition theorem from the linearity of the automatic equalizer that it is given by the product of the square value of and the power of the received signal input to the automatic equalizer. In the receiver, the power of the received signal input to the automatic equalizer is usually kept approximately constant by the automatic gain control circuit in the preceding stage, so the amount of increase in the equivalent residual error power is, after all, Proportional to the squared value of the tap coefficient before being forced to zero.

On the other hand, it is known that the square value of the tap coefficient of an automatic equalizer generally gradually decreases as it moves away from the center tap.

Therefore, among the taps of the automatic equalizer, the sum of the squared values of the tap coefficients of the taps on the leftmost side and the same number of taps on the rightmost side is calculated, and these values CL and c
By comparing with R, the positional force of center tap □
This allows you to know whether the image is deviated from the correct position.

From the standpoint of minimizing the equivalent residual error power, cL
= cR is desirable, but from the standpoint of shortening delay time and improving throughput, some CL>c
Even if the state R is allowed, that is, a slight increase in the equivalent residual error power is allowed, it is more effective to move the center tap to the left.

Conversely, if for some reason the center tap is too far to the left, resulting in a state where CL >> CR, the throughput will be affected by an increase in the bit error rate due to an increase in equivalent residual error power rather than a decrease in delay time. The center tap should be moved to the right in such a case, since it will decrease due to the effect.

The operation of moving the center tap to the left or right is
This can be done by shifting all tap coefficients one step to the left or right.

Through the above-described operations, an automatic equalizer with a delay time as short as possible can be realized.

〔Example〕

FIG. 1 is a diagram showing an embodiment of the present invention.

This automatic equalizer includes, for example, a shift register 1 in which a plurality of stages of delay type flip-flops are connected in cascade, a shift register 2 in which delay type flip-flops having the same number of stages are connected in cascade, and a multiplier 3. ,6,7.8.9,1
0.11, adder 12, squarers 13, 14, 15 and 16, 17, 18, adders 19, 20, 21,
It is composed of a determiner 22.

The shift register 1 shifts the received signal input to the input terminal 23 to the right by one stage every baud period.

The soft register 2 stores tap coefficients in each stage. Multipliers 3 to 11 multiply the tap coefficient of each stage of shift register 2 by the output from each stage of shift register 1. The adder 12 adds the multiplication results and outputs the result from the output terminal 24 as an output of the automatic equalization layer. Squarer 13.14.
15 calculates the square of each tap coefficient of the leftmost three taps of the shift register 2.

On the other hand, the squarer 16, 17, 18 calculates the square of each tap coefficient of the rightmost three taps of the shift register 2.

Adder 19 calculates the sum cL of the outputs of squarers 13, 14 and 15, and adder 20 calculates the sum cL of the outputs of squarers 13, 14 and 15.
Calculate the sum CR of the outputs of 8. Adder 21 is adder 1
The output cR of the adder 20 is subtracted from the output CL of the adder 9.

The determiner 22 checks the value of the output of the adder 21, and if this value is greater than a certain threshold value, it supplies a shift pulse to shift the shift register 2 by one stage to the right. Further, when the output of the adder 2 is smaller than another threshold value that is slightly smaller than the threshold value, the determiner 22 determines that:
A shift pulse is supplied to shift the shift register 2 by one stage to the left.

Next, the operation of this embodiment will be explained.

When the received signal is input to the shift register 1 via the input terminal 23, the shift register 1 shifts the input received signal one stage to the right every baud period. Squarer 1.3
．． 14.15 calculates the square of each tap coefficient of the left terminal 3 taps of the shift register 2, and the adder 19 calculates the sum cl- of the outputs of these squarers. On the other hand, squarer 16.1
7.18 calculates the square of each tap coefficient of the rightmost three taps, and the adder 20 calculates the sum cR of the outputs of these squarers.

The adder 21 subtracts the output cR of the adder 20 from the output cL of the adder 19 and sends the value to the determiner 22.

In the determiner 22, when this value is larger than a certain threshold value, a shift pulse is supplied so that the shift register 2 is shifted one increment to the right. As a result of this shift, the rightmost tap coefficient is lost and the leftmost tap coefficient is “
0" is input. Further, when the value of the output of the adder 21 is smaller than another threshold value that is slightly smaller than the threshold value, the determiner 22 moves the shift register 2 one stage to the left. As a result of this shift I, the leftmost tap coefficient is lost, and "0" is input to the rightmost tap coefficient.

As a result of the above, the use of the rightmost or leftmost tap of the shift register 2 is stopped, and as a result, the delay time of the automatic equalizer is reduced by one tap stage.

〔Effect of the invention〕

As described above, according to the present invention, an automatic equalizer with a delay time as short as possible is realized, so that the transmission delay time of the modulation/demodulation device is reduced, and as a result, throughput can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. ■, 2...Shift register 3 to 11... Multiplier 12, 19-21... Adder 13-18...Squarer 22...Judgment device

Claims (1)

[Claims] (1) in an automatic equalizer having taps, a first means for calculating the sum of squares of tap coefficients of several taps closest to the input end among the taps of the automatic equalizer;
a second means for calculating the sum of the squares of the tap coefficients of the same number of taps on the side closest to the input end and the same number of taps on the side furthest from the input end; and means for subtracting the output value of the second means; and means for determining the magnitude of the subtracted value, and when the subtracted value is greater than a predetermined threshold, all the tap coefficients are An automatic equalizer characterized in that it shifts by one stage to the side farthest from the input end, and when the value is smaller than another threshold value that is slightly smaller than the threshold value, it shifts by one stage to the side closest to the input end. .