JPS6333039A - Processing and communicating equipment for double programmable bidirectional data - Google Patents

Abstract

PURPOSE:To easily and rapidly process bidirectional data different in speed of high and low by changing over alternately at the speed higher than both the processing of the data having a mutually different speed by using a program for processing high speed data and a program for low speed data. CONSTITUTION:An arithmetic circuit 18 changes over alternately a program 182 for processing high speed data and a program 183 for processing low speed data by a changing-over signal EX from a clock generating circuit 162 for one step of the data processing procedure respectively, inputs always the value of a corresponding timer 141 for high speed data and a timer 151 for low speed data through a bus 17 as data, detects, inputs the data from the external part, processes and outputs. High speed data inputted from an ascending high speed data line HUP, after they are processed by the program 182, are stored into a RAM 131, and thereafter, outputted to an ascending low speed data line LUP by the program 183 as the low speed data. Consequently, the flow of the ascending data is as shown in the broken line arrow UP. In the same way, the flow of the descending data is as shown in the broken line arrow DN.

Description

[Detailed Description of the Invention] [Summary] This is a dual programmable bidirectional data processing communication device, which uses a high-speed data processing program to process data having mutually different speeds regarding bidirectional data consisting of uplink data and downlink data. and a low-speed data processing program, which are alternately switched.

[Industrial application field]

The present invention provides two terminals 1' as shown in FIG. 8(A).
A double programmable bidirectional data processing communication device 2 with a program that processes bidirectional data of uplink data UP and downlink data DN, which have different transmission directions, in accordance with their respective data speeds when data is exchanged between and 6'. ', 5
'Regarding.

In the bidirectional data communication system described above, a high-speed data line 7' is connected between the bidirectional data processing and communication devices 2' and 5', and each device 2', 5' and their terminal 1'.

6' are connected by low-speed data lines LUP and LDN, respectively, but line termination circuits 3' and 4' are used to reduce the number of high-speed data lines 7' to one, increasing economical efficiency.

However, from the perspective of each bidirectional data processing communication device, this means that the data speeds on the terminal side and the opposite data processing communication device side are different.

For example, regarding the bidirectional data processing communication device 5', high-speed data inputted from the uplink high-speed data line HUP (FIG. 8 (B-a)) and high-speed data outputted to the downlink high-speed data line HDN (FIG. 8(B-a)) (B-b)) is the low-speed data input from the downlink low-speed data line LDN (Fig. 8 (B-b)).
c)) is twice the speed of the low-speed data (FIG. 8 (B-d)) output to the upstream low-speed data line LUP.

The constraints in this case are: first, high-speed data (HOP, HDN) and low-speed data (LIIP,
Second, in these high-speed and low-speed data, upstream data (IIU) must be processed.
P.

LUP) and downlink data (HDN, LDN) must be processed in both directions, and thirdly, the points at which these data pass through points A, B, C, and D are uncertain. etc.

Therefore, in the two-way data communication system (Fig. 8 (A)')
,The problem is how to efficiently process data under these,constraints.

[Conventional technology]

There are two conventional data processing and communication devices (Figures 6 and 7).

In the first prior art (FIG. 6), serial data is input to a data separation circuit I', the data is distributed and divided, and stored in a buffer memory 4', and processing circuits 5' and 6
After performing predetermined processing in ', the multiplexing circuit 9' multiplexes and outputs the data. In Figure 6, 21
3' is a frame synchronization circuit, 3' is a PLL circuit that generates a clock whose phase is synchronized with the internal clock in order to read input data accurately, 7' is a clock generator that supplies clocks to each circuit, and 81 is its mask clock generator. , 10
1 is a frame pattern generation circuit that generates a frame to be added to output serial data.

The device shown in FIG. 6 has a problem in that since it is entirely constructed of hardware, it has to be rebuilt even if the frame synchronization pattern changes slightly or the data format changes, making it less versatile.

A second conventional technique shown in FIG. 7 has been proposed to solve this problem.

In FIG. 7, input serial data is converted into parallel data by the serial/parallel conversion circuit 12, taken into the bus 72, stored in the RAM 52, processed by the arithmetic circuit 52+ of the CPU 6'', and then processed by the parallel/serial conversion circuit 22. It is serially converted and output.

Program 6 that processes these data on CPU 6"
Everything is done using z2.

In FIG. 7, 32 is a PLL circuit that generates a clock whose phase is synchronized with the internal clock to read data correctly, and 42 is a mask clock generator 72.
This is a clock generator that divides the frequency of the clock from the circuit and supplies a predetermined clock to each circuit. The program 6I consists of a sequencer 6zz+1 program ROM 6"" and an instruction execution circuit 6223, and is stored in the ROM while the sequencer 622' controls the address of the program ROM 6222.

The program is passed to the instruction execution circuit 6223, and each circuit executes a data processing procedure according to the program.

According to this second prior art, even if the data communication method changes, this can be handled by simply changing the program, so the problems of the first prior art have been solved.

[Problem that the invention seeks to solve]

The conventional data processing communication device shown in FIG. 7 processes data using one program 622.

However, one program can only process data at the same speed, and often has difficulty processing data at different speeds. For example, the number of operations such as CPU interrupts increases, making the program itself complex and difficult to implement. Therefore, it cannot be applied to the communication system that requires simultaneous processing of high-speed data and low-speed data as described in FIG. 8(A).

Furthermore, in FIG. 8(A), both high-speed data and low-speed data are processed in both up and down directions, but it is difficult to apply the second prior art to such a two-way data processing method. For example, two devices shown in FIG. 7 must be provided.

That is, in the past, there was a problem in that it was not easy to process both high-speed data and low-speed data simultaneously in both directions.

[Means for solving problems]

An object of the present invention is to solve the above-mentioned problems and to easily and quickly process bidirectional data consisting of uplink and downlink high speed data and uplink and downlink low speed data.

As shown in FIG. 1, means for this purpose include a high-speed data input/output section 11 to which an uplink high-speed data line and a downlink high-speed data line are connected, and a low-speed data input/output unit 11 to which a downlink low-speed data line and an uplink low-speed data line are connected. section 12, a data storage section 13 that stores high-speed data and low-speed data, a high-speed data input/output time measuring section 14 that measures the input/output time of high-speed data in the high-speed data input/output section, and low-speed data in the low-speed data input/output section. It has a low-speed data input/output time measuring section 15 that measures the input/output time of the data, a clock generating section 16 that supplies clocks to each section, an arithmetic circuit 181 that processes the high-speed data and low-speed data, and a high-speed data processing program 182 and a low-speed data processing program 182. Central processing unit 1 provided with a data processing program 183
8 and 8 are connected to each other by a bus 17, and both programs 1 are executed at a faster speed than the high-speed data and low-speed data by the switching signal EX from the clock generator 16.
82 and 183 alternately, so that the high-speed data processing program 182 processes only high-speed data, and the low-speed data processing program 183 processes only low-speed data, respectively. This is a communication device 1.

[For production]

As described above, according to the present invention, bidirectional data processing can be easily performed by alternately switching between two programs.

That is, a high-speed data processing program 182 and a low-speed data processing program 183 are provided, and these programs are
At a speed (Fig. 3 (E) (F)) that is faster than both the high speed data speed (Fig. 3 (A) (B)) and the low speed data speed (Fig. 3 (C) (D)), For each step (4th
(Fig. 5) By monitoring the high-speed data human output time measurement unit 14 and the low-speed data input/output time measurement unit 15 separately while switching them alternately, it is possible to perform predetermined data processing at preset input/output times. can.

〔Example〕

The present invention will now be described by way of examples and with reference to the accompanying drawings.
explain.

FIG. 2 is a diagram showing an embodiment of the present invention.

The dual programmable bidirectional data processing and communication device 1 shown in FIG.
2. Data storage unit 13, high-speed data input/output time measurement unit 1
4, consists of a low-speed data input/output time measurement section 15, a clock generation section 16, and a central processing section 18, which are connected to a path 17.
connected by.

The high-speed data input/output section 11 consists of a high-speed data serial-to-parallel conversion circuit 111 and a high-speed data parallel-to-serial conversion circuit 112, the former being connected to the uplink high-speed data line HUP, and the latter connected to the downlink high-speed data line HDN. The up high speed data line HUP and the down high speed data line HDN are each connected to one bidirectional high speed data line 3 via a line termination circuit 2.

On the other hand, the low-speed data input/output unit 12 consists of a low-speed data parallel-to-serial conversion circuit 121 and a low-speed data serial-to-parallel conversion circuit 122, the former being connected to the uplink low-speed data line LUP, and the latter connected to the downlink low-speed data line LDH. , this LUP and LDN are both connected to the terminal 4.

The data storage unit 13 includes a RAM 131, the high-speed data input/output time measuring unit 14 includes a high-speed data timer 141, and the low-speed data input/output time measuring unit 15 includes a low-speed data timer 151.

In the data storage unit 13, after one program (for example, a high-speed data processing program 182), which will be described later, reads high-speed data from the high-speed data serial/parallel conversion circuit 111 and processes it, this high-speed data is treated as low-speed data and stored as the other low-speed data. Since it is processed by the processing program 183,
It is provided to temporarily store high-speed data after this processing.

The clock generator 16 generates a clock signal PLL (Phase L
(lockedLoop) circuit 161, clock generation circuit 1
62 and a master crofter generator 163.

The PLL circuit 161 includes a clock for high-speed data and low-speed data input from outside the device 1, and the clock generation circuit 16.
Synchronize the phase with the internal clock generated in step 2. The clock generation circuit 162 includes a mask clock generator 163.
The clock from the device 1 is inputted, frequency-divided, and a predetermined clock is sent to each circuit inside the device 1.

The central processing unit 18 includes an arithmetic circuit 181, a high-speed data processing program 182, and a low-speed data processing program 183.
, and processes high-speed data and low-speed data that are input to and output from the device 1, which includes an inverter 184.

The arithmetic circuit 18 starts a high-speed data processing program 182 and a low-speed data processing program 183, and processes data based on the instructions of these two programs.

The high-speed data processing program 182 and the low-speed data processing program 183 are switched by a program switching signal EX sent from the clock generation circuit 162.

This switching signal EX is set at a high speed data rate (Fig.
, (B)) and the speed of low-speed data (Fig. 3 (C) (
D)) is a signal consisting of pulses that change at a much faster rate than either of the following (Fig. 3(E) and (F)).

Each program 182 and 183 is connected to the sequencer 18.
23, 1833, program ROM11322, 1
832 and instruction execution circuits 1821 and 1831. Sheega, Nsa 1823°1833 are compatible programs R
The addresses of the OMs 1822 and 1832 are sequentially searched, and the program ROMs 1822 and 1832 store a program for processing high-speed data in the former and a program for processing low-speed data in the latter at the predetermined addresses, respectively, and the instruction execution circuit 1831, 1831 inputs and outputs data between each circuit via bus 17, transfers data, performs calculations, etc. by inputting programs from program ROMs 1822 and 1832 and executing the contents thereof.

Hereinafter, the operation of the dual programmable bidirectional data processing and communication device 1 having the above configuration will be explained based on FIGS. 3 to 5.

First, two programs 182 and 183 are activated by the arithmetic circuit 181, and the high-speed data timer 141 is activated.
and the low-speed data timer 151 is set.

That is, in the high-speed data timer 141, the input time is "7" and the output time is "9" (FIG. 4), and in the low-speed data timer 151, the input time is "3" and the output time is "5". ” (Fig. 5), respectively.

All operations starting from setting the timer to inputting, processing, and outputting data are performed based on two programs 182 and 183 that switch alternately (Fig. 3 (E) and (F)). ). In other words, both the high-speed data processing program 182 and the low-speed data processing program 183 are executed at each step (fourth step) of the data processing procedure.
(Fig. 5) Alternately switched by the switching signal (Fig. 3 (E) (F)), always corresponding timers 141 and 1
51 is input as data via the bus 17, it is detected, and high data and low speed data are input from the outside, processed, and output.

For example, the high-speed data processing program 182 looks at the time measured by the high-speed data timer 141 and determines the input time and
That is, if it becomes "7" (Fig. 4), at the next switching point (Fig. 3 (E)), it is input from the uplink high-speed data line HUP to the high-speed data serial/parallel conversion circuit 111 and is converted into parallel data. High-speed data is taken into the bus 17 at a high speed of 8 bits, and the data is received (FIG. 4). If this high-speed data needs to be processed, it is input to the arithmetic circuit 181, subjected to predetermined processing, and then stored in the RAM 131 (FIG. 4).

After being stored in this RAM 131, it is output as 8-bit 172 4-bit low-speed data from the low-speed data parallel-to-serial conversion circuit 121 to the upstream low-speed data line LUP.
The other low-speed data processing program 183 handles the processing.

Regardless of this, the high-speed data processing program 182
The timer continues to watch the time measured by the high-speed data timer 141 while switching alternately (Fig. 3 (E)), and that time becomes the output time (Fig. 4), that is, "9". In case(
3(B)), the 8-bit high-speed data serially converted in the high-speed data parallel-to-serial conversion circuit 112 is output to the downlink high-speed data line HDN, and the data transmission operation is completed (FIG. 4).

At the next switching point (FIG. 3(E)), the high-speed data processing program 182 increases the set values of the high-speed data timer 141 by 8 from the previous time to "15" and "1".
7'' (Fig. 3 (A), (B), Fig. 4), and at this time, perform the same operation as the previous time.

The high-speed data processing program 182 repeats the above operations (FIG. 4).

Further, the low-speed data processing program 183 also checks the time measured by the low-speed data timer 151, and when it reaches the manual time (FIG. 5), that is, "3" (FIG. 3(C)),
The low-speed data input from the downlink low-speed data line LDN to the low-speed data serial/parallel conversion circuit 123 and converted into parallel data is
The data is received on the bus 17 at a low speed of 4 bits (Fig. 5).

At the next switching point (FIG. 3(F)), the arithmetic circuit 181
The low-speed data is processed at the next switching point, and the low-speed data is stored in the RAM 131 (FIG. 5).

The low-speed data stored in the RAM 131 is then output from the high-speed data parallel-to-serial conversion circuit 112 to the downlink high-speed data line HDN as 8-bit high-speed data, so that it is sent to the other high-speed data processing program 182. The processing is entrusted to them (Figure 4).

The low-speed data processing program 183 uses its timer 15.
When the value of 1 reaches the output time, that is, "5", the serially converted low-speed data is output from the low-speed data parallel-to-serial conversion circuit 121 to the upstream low-speed data line LUP, and the data transmission operation ends (FIG. 5).

Thereafter, the input time and output time of the low-speed data timer 151 are added by 4 to become "7" and "9", as in the high-speed data processing program 182. This operation is repeated (Fig. 5).

In the embodiment of FIG. 2 described above, the uplink high-speed data line H
The high-speed data input from UP is processed by the high-speed data processing program 182 and then stored in the RAM 131, and then output as low-speed data to the upstream low-speed data line LUP by the low-speed data processing program 183. Therefore, the flow of upstream data is as shown by the broken line arrow UP when looking only at the high-speed data serial-to-parallel conversion circuit 111 and the low-speed data parallel-to-serial conversion circuit 121.

Similarly, the flow of downstream data is shown by the broken line arrow DN if only the low-speed data serial-to-parallel conversion circuit 123 and the high-speed data parallel-to-serial conversion circuit 112 are considered.

〔Effect of the invention〕

As described above, according to the present invention, by alternately switching between a high-speed data processing program and a low-speed data processing program, the former is used to process only high-speed uplink data and downlink data, and the latter is used to process only low-speed uplink data and downlink data. can be processed independently.

Therefore, bidirectional data with different high and low speeds,
The process can now be done more easily and quickly than before.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is an explanatory diagram of the operation of the present invention, and FIG. 4 is a data processing procedure of a high-speed data processing program according to the present invention. , FIG. 5 is a diagram showing the data processing procedure of the low-speed data processing program according to the present invention, FIG. 6 is an explanatory diagram of the first prior art, FIG. 7 is an explanatory diagram of the second prior art, and FIG. The figure is an explanatory diagram of the industrial application field. DESCRIPTION OF SYMBOLS 1... Dual programmable bidirectional data processing communication device, 11... High speed data input/output section, 12... Low speed data input/output section, 13... Data storage section, 14... High speed data input/output section Time measurement unit, 15...Low speed data input/output time measurement unit, 16...Clock generation unit, 17...Bus, 18...Central processing unit,
181...Arithmetic circuit, 182...Program for high-speed data processing, 183...Program for low-speed data processing, +1UP...Uplink high-speed data line, HDN...Download high-speed data line, LUP...Uplink Low speed data line, LDN...low speed down data line. Figure 11: High-speed data input/output section 12... Low-speed data input/output section 15,... Low-speed data input/output time measurement section] 6... Clock generation section 17. ...Bus 18...Central processing unit]8]...Arithmetic circuit 182...High-speed data processing program 183...
Low-speed data processing program HUP...Uplink high-speed data line HDN...Download high-speed data line LUP...Uplink low-speed data line LDN...Download low-speed data line Data processing procedure of the high-speed data processing program according to the present invention Figure V, Figure 4 shows the data processing procedure of the low-speed data processing program according to the present invention.

Claims (1)

[Claims] A high-speed data input/output unit (11) to which an uplink high-speed data line and a downlink high-speed data line are connected; a low-speed data input/output unit (12) to which a downlink low-speed data line and an uplink low-speed data line are connected; A data storage section (13) that stores high-speed data and low-speed data
), a high-speed data input/output time measuring unit (1) that measures the input/output time of high-speed data in the high-speed data input/output unit (11);
4), a low-speed data input/output time measuring unit (1) that measures the input/output time of low-speed data in the low-speed data input/output unit (12);
5), a clock generation section (16) that supplies clocks to each section, and an arithmetic circuit (181) that processes the high-speed data and low-speed data.
) and a high-speed data processing program (182
) and a low-speed data processing program (183) are connected to each other by a bus (17), and the high-speed data and low-speed data processing programs are connected to each other by a bus (17). The programs for high-speed data processing (
182) is a dual programmable bidirectional data processing communication device characterized in that a low speed data processing program (183) is designed to process high speed data, and a low speed data processing program (183) is designed to process low speed data.