JPS63316140A - Logic simulator - Google Patents

Logic simulator

Info

Publication number
JPS63316140A
JPS63316140A JP15191787A JP15191787A JPS63316140A JP S63316140 A JPS63316140 A JP S63316140A JP 15191787 A JP15191787 A JP 15191787A JP 15191787 A JP15191787 A JP 15191787A JP S63316140 A JPS63316140 A JP S63316140A
Authority
JP
Japan
Prior art keywords
input
event
11w1m
part
logic simulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15191787A
Inventor
Hajime Asano
Yasuyuki Kanazawa
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Priority to JP15191787A priority Critical patent/JPS63316140A/en
Publication of JPS63316140A publication Critical patent/JPS63316140A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To prevent the overflow of a logic simulator of time independent system from being generated, by stopping or limiting input other than required input to a logical simulation processor, etc., by providing a bus arbitration part.
CONSTITUTION: An input event supplying part 4 sets a control signal 6 at true at the time of outputting an input event and issues an output request to the bus arbitration part 7. Similarly, each of the logical simulation processor 11W1m also sets a corresponding control signal of the control signals 21W2m at the true before outputting the event, and issues the output request to the arbitration part 7. And the input of the input event from the supplying part 4 to the processors 11W1m is permitted only when the signals 21W2m are false, and when either the processors 11W1m outputs the event, the supplying of a sky event is stopped, and the input other than the required one is stopped or limited, thereby, it is possible to prevent the overflow of the logic simulator of time independent system which performs a parallel fast processing with a simple constitution from being generated.
COPYRIGHT: (C)1988,JPO&Japio
JP15191787A 1987-06-18 1987-06-18 Logic simulator Pending JPS63316140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15191787A JPS63316140A (en) 1987-06-18 1987-06-18 Logic simulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15191787A JPS63316140A (en) 1987-06-18 1987-06-18 Logic simulator

Publications (1)

Publication Number Publication Date
JPS63316140A true JPS63316140A (en) 1988-12-23

Family

ID=15529021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15191787A Pending JPS63316140A (en) 1987-06-18 1987-06-18 Logic simulator

Country Status (1)

Country Link
JP (1) JPS63316140A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04227574A (en) * 1990-03-30 1992-08-17 Internatl Business Mach Corp <Ibm> All event trace gatherer for logic simulation machine
JPH05205005A (en) * 1990-03-30 1993-08-13 Internatl Business Mach Corp <Ibm> Host interface for logic simulation machine

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5971554A (en) * 1982-10-15 1984-04-23 Matsushita Electric Ind Co Ltd Digital circuit simulator
JPS60116059A (en) * 1983-11-29 1985-06-22 Fujitsu Ltd Bus controlling system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5971554A (en) * 1982-10-15 1984-04-23 Matsushita Electric Ind Co Ltd Digital circuit simulator
JPS60116059A (en) * 1983-11-29 1985-06-22 Fujitsu Ltd Bus controlling system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04227574A (en) * 1990-03-30 1992-08-17 Internatl Business Mach Corp <Ibm> All event trace gatherer for logic simulation machine
JPH05205005A (en) * 1990-03-30 1993-08-13 Internatl Business Mach Corp <Ibm> Host interface for logic simulation machine

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