JPS63309021A - Voltage comparator - Google Patents

Abstract

PURPOSE:To extremely reduce the power consumption of a pull-up resistor while maintaining fast operation by using two open drain type comparators and two PNP transistors (P-channel FET), and obtaining an H-level and an L-level output through the switching both operation. CONSTITUTION:When such voltages V1 and V2 that V1<V2 are applied to input terminals 10 and 11, a comparator 9 is ON (low level L output state), a comparator 8 OFF (high level H output state), a TR 2 ON, and a TR 3 OFF stably. When V1>V2, on the other hand, the comparator 9 is OFF, the compara tor 8 ON, the TR 2 OFF, and the TR 3 ON stably. Therefore, when V1<V2, the output voltage V0 of an output terminal 12 is L (=0V) and when V1>V2, V0=H (=VDDV), so that a current flows to a resistor 1 in neither state.

Description

Detailed Description of the Invention [Field of Industrial Application] This invention relates to a voltage comparison circuit used in a pulse receiving circuit etc. in digital communication, and particularly relates to a voltage comparison circuit using an open drain (or open collector) type comparator. .

"Prior Art" Conventionally, this type of voltage comparison circuit has an open drain (or open collector) type comparator 21 and a pull-up resistor connected between its output terminal 28 and power supply terminal 27, as shown in FIG. It was composed of a container 22. Voltage ■1 input to the non-inverting input terminal 23 of the comparator 21 and voltage V2 input to the inverting input terminal 24
are compared by the comparator 21, and the result is output to the output terminal 28.

"Problems to be Solved by the Invention" The conventional voltage comparison circuit described above sets the potential of the non-inverting input terminal 23 to v,[Vl, and the potential of the inverting input terminal 24 to v2Il.
vl, the potential of the output terminal 28 vO (vll, l'/'
77 /'Resistance value of resistor 22 is RO times, power supply terminal 2
Assuming a potential of 7 or DDM, when Ml<V2, Vo=O, a current flows to the pull-up resistor 22, and power is consumed by the pull-up resistor 22.

One method for reducing the power consumption in the pull-up resistor 22 is to increase the resistance value of the pull-up resistor 22. However, since there is generally a stray capacitance C8 between the output terminal 28 and the negative power supply input terminal 26, when the state changes from the state of Vl (V2) to the state of Vl)V2, the output A 1-broad edge occurs in the rising edge of the output waveform of the terminal 28, and an increase in the resistance value of the pull-up resistor 22 worsens this 1-blind curve.

Therefore, especially when high-speed operation is required in such a voltage comparator circuit, the resistance value RO of the pull-up resistor 22 cannot be made very large, and the power consumption po in the pull-up resistor 22 becomes large. There is a drawback of Shima 5.

"Means for solving the problem" The voltage comparator circuit of the present invention has a first terminal connected to a power supply at one end.
a first PNP transistor (first P-channel FET) and a second PNP transistor (second P-channel FET) whose emitter terminal (source terminal) is connected to the other end of the first resistor. ), one end is connected to the base terminal (gate terminal) of the first PNP transistor (first P-channel FET), and the other end is connected to the collector terminal (drain terminal) of the second PNP transistor (second P-channel FET). one end is connected to the base terminal (gate terminal) of the second PNP transistor (second P-channel FET), and the other end is connected to the first capacitor (terminal). PNP transistor (first P-channel FE
The third terminal connected to the collector terminal (drain terminal) of T)
a resistor and a second capacitor, and a first open-drain (or open-collector) type comparator whose output terminal is connected to the collector terminal (drain terminal) of the first PNP transistor (first P-channel FET). , the output terminal is connected to the collector terminal (drain terminal) of the second PNP transistor (second P-channel FET), and the non-inverting input terminal is connected to the inverting input terminal of the first comparator/parator, and , and a second open drain (or open collector) type comparator whose inverting input terminal is connected to the non-inverting input terminal of the first comparator.

"Example" Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This voltage comparison circuit includes a first resistor 1 whose one end is connected to a power supply, and a first resistor 1 whose emitter terminal is connected to the other end of the first resistor 1.
a PNP transistor 2 and a second PNP transistor 3; and a second resistor 4 whose one end is connected to the base terminal of the first PNP transistor 2 and the other end is connected to the collector terminal of the second PNP transistor 3. and a first capacitor 5, a third resistor 6 and a second capacitor, one end of which is connected to the base terminal of the second PNP transistor 3, and the other end of which is connected to the collector terminal of the first PNP transistor 2. 7, a first open-drain (or open; collector) type comparator 8 whose output terminal is connected to the collector terminal of the first PNP transistor 2; and a first open-drain (or open; collector) type comparator 8 whose output terminal is connected to the collector terminal of the second PNP transistor 3. , and a second open drain (or an open collector) type comparator 9, a non-inverting input terminal 10 is derived from the inverting input terminal of the first comparator 8, and an inverting input terminal 11 is derived from the non-inverting input terminal,
An output terminal 12 is led out from the output terminal of the second comparator 9.

Next, the operation of this voltage comparison circuit will be explained.

In FIG. 1, first consider the state in which the voltages Vl and V2 applied to the input terminals 10 and 11 are Vl<V2. Comparator 9: ON (output is at low level "L" state) Comparator 8: 0FF ( Transistor 2: ON Transistor 3: OFF Stable state. At this time, an equivalent circuit can be drawn by simply replacing transistors 2 and 3 and comparators 8 and 9 (output stage transistors) with switches as shown in Figure 2 (al
becomes.

Further, considering the state of Vl>■2 in FIG. 1, the comparator 9: OFF, the comparator 8: ON, the transistor 2: OFF, and the transistor 3: ON become stable. At this time, if we draw an equivalent circuit by simply replacing transistor 2゜3 and comparators 8 and 9 (output stage transistors) with switches, we get Figure 2 (b).
).

As is clear from FIGS. 2(a) and (b), Vt (V
2, the output voltage VO of the output terminal 12 is ■0-"L" (
=0(V:)), and when Vl>V2, Vo-“H”(
-VDD (V)), and no current flows through resistor 1 in any stable state. In addition, in Figure 1,
Capacitor 5 and capacitor 7 have Vo=“H” and Vo
- It is a speed-up capacitor to make the change from "L" quick, and resistor 1 = "H"
= "L" This is a resistor for limiting the current between VDD and OV at the moment of topographic change.

"Effects of the Invention" As explained above, the present invention provides an oven-dray yc or open collector type comparator and a PNP type comparator.
By using two transistors each, a 1H "level" and "IIL" level output can be obtained by the switching operation of both transistors, and the power consumption in the pull-up resistor can be extremely reduced while maintaining high-speed operation.

Note that a P-channel FET is used instead of a PNP transistor.
A similar effect can be obtained by changing the emitter terminal to the source terminal, the base terminal to the gate terminal, and the collector terminal to the drain terminal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the voltage comparison circuit of the present invention, FIG. 2 is an explanatory diagram showing an outline of the operation of the voltage comparison circuit of the invention, and FIG. 3 is an example of a conventional voltage comparison circuit. The circuit diagram and FIG. 4 are explanatory diagrams showing operating waveforms of a conventional voltage comparison circuit. 1 Figure DD Inverting input hole 2 SOO

Claims (1)

[Claims] (1) A first resistor whose one end is connected to a power supply, and a first PNP transistor (first P-channel F) whose emitter terminal (source terminal) is connected to the other end of the first resistor.
ET) and a second PNP transistor (second P-channel FET), one end of which is connected to the base terminal (gate terminal) of the first PNP transistor (first P-channel FET), and the other end of which is connected to the base terminal (gate terminal) of the first PNP transistor (first P-channel FET). a second resistor connected to the collector terminal (drain terminal) of the second PNP transistor (second P-channel FET) and a first capacitor connected in parallel to the second resistor; is connected to the base terminal (gate terminal) of the second PNP transistor (second P-channel FET), and the other end is connected to the collector terminal (drain terminal) of the first PNP transistor (first P-channel FET). a third resistor connected to the terminal) and a second capacitor connected in parallel to the third resistor; and the output terminal is the collector terminal of the first PNP transistor (first P-channel FET). (drain terminal) of the first open drain (or open collector) type comparator;
connected to the collector terminal (drain terminal) of the transistor (second P-channel FET), and whose non-inverting input terminal is connected to the inverting input terminal of the first comparator;
and a second open drain (or open collector) type comparator whose inverting input terminal is connected to the non-inverting input terminal of the first comparator, and the inverting input terminal is connected to both input terminals of the first comparator. and a voltage comparison circuit from which a non-inverting input terminal is derived, and an output terminal is derived from the output terminal of the first comparator or the second comparator.