JPS63308966A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63308966A JPS63308966A JP14559587A JP14559587A JPS63308966A JP S63308966 A JPS63308966 A JP S63308966A JP 14559587 A JP14559587 A JP 14559587A JP 14559587 A JP14559587 A JP 14559587A JP S63308966 A JPS63308966 A JP S63308966A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- layer
- channel transistor
- impurity
- mixed crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000013078 crystal Substances 0.000 claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 21
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 239000004047 hole gas Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 8
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 38
- 230000000295 complement effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は二次元状態に分布する高移動度のホール及び電
子の流れをゲートｒｒ１極によって制御する相補型変調
ドーピングへテロ接合トランジスタの構造に関する。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to the structure of a complementary modulation doping heterojunction transistor in which the flow of high-mobility holes and electrons distributed in a two-dimensional state is controlled by a gate rr1 pole. .
変調ドーピング超格子構造は１９７０年、Ｅｓａｋｉら
によって提案され、１９７８年、Ｄｉｎｇｉｅらによっ
て、Ｇ ａ Ａ ｓ ／ Ａρｘ Ｇ ａ 、ＸＡｓ系
でそれが実現された。その後、変調ドーピング単一へテ
ロ接合に於いても２次元電子ガス及び２次元ホールガス
の存在が確認されている。とくに、Ｓ ｉ／Ｇｅ ｘＳ
ｉ＋−ｘ系では、電子移動度だけでな（、ホールの移
動度も大きいため、相補型トう／ジスタとして注目を集
めており、ｎチャネルトランジスタ（ＩＥＥＥ、 Ｔ
ｒａｎｓａｃｔｊｏｎｓ ｏｎ ｅｌｅｃｔｒ
ｏｎ ｄｅｖｊｃｅｓ、 Ｖｏｌ ＥＤ−
３３，Ｎｏ、 ５． １９８６、Ｐ８３３）や、ｎチ
ャネルトランジスタ（ＩＥＥＥ、 Ｅｌｅｃｔｒｏ
ｎ ｄｉｖｉｃｅｌｅｔｔｅｒｓ、 Ｖｏｌ、
ＥＤＬ−７，ＮＯ，５，１９８６，Ｐ２Ｏ３）の試作
が行なわれている。相補型の２次元キャリアガスを用い
た素子に関しては、特許出願公開、昭−ＣｉＯ−２６３
４７１等があった。A modulated doping superlattice structure was proposed by Esaki et al. in 1970, and Dingie et al. realized it in 1978 in the GaAs/AρxGa,XAs system. After that, the existence of two-dimensional electron gas and two-dimensional hole gas was confirmed even in a modulation-doped single heterojunction. In particular, Si/Ge xS
In the i + -
ransactjons on electr
on devjces, Vol ED-
33, No, 5. 1986, P833) and n-channel transistors (IEEE, Electro
n diviceletters, Vol.
EDL-7, NO, 5, 1986, P2O3) is being prototyped. Regarding elements using complementary two-dimensional carrier gas, patent application publication, Sho-CiO-263
There was a 471st mag.
しかし、変調ドーピングは結晶成長時に限り行なうこと
が可能であるために、同一基板上へｐ型とｎ型の変調ド
ーピングを行うためには、少なくとも２０の結晶成長工
程が必要とされる。このことは、相補型トランジスタの
形成を困難にするばかりでなく、スループットが小さい
ヘテロエピタキシャル装置に大きな負担となる。さらに
、ｓｉ／ＧｅｘＳｉｔ−Ｘ系では、ＧａＡｓ／ＡρｘＧ
ａ、−ｘＡｓ系より、ホールの移動度が太き（できるに
もかかわらず、ｎチャネルトランジスタとｎチャネルト
ランジスタの構造が異なりすぎているために、すなわち
、２次元電子ガスはシリコン層中に、２次元ホールガス
はシリコン−ゲルマニウム混晶層中へ存在させる必要上
、相補型のトランジスタを実現を困難なものとしている
。However, since modulation doping can be performed only during crystal growth, at least 20 crystal growth steps are required to perform modulation doping of p-type and n-type on the same substrate. This not only makes it difficult to form complementary transistors, but also places a heavy burden on heteroepitaxial devices with low throughput. Furthermore, in the si/GexSit-X system, GaAs/AρxG
Although the hole mobility is higher than that of the a, -xAs system, because the structures of n-channel transistors and n-channel transistors are too different, in other words, the two-dimensional electron gas is The two-dimensional hole gas must exist in the silicon-germanium mixed crystal layer, making it difficult to realize a complementary transistor.
本発明はこのような問題点を解決するもので、その目的
とするところは、低消費電力でしかも高速動作可能な相
補型トランジスタとして好適な、２次元電子及び２次元
ホールガスを利用した２種類のトランジスタを同一基板
上に形成するために適当な構造をもつ半導体装置を提供
することにある。The present invention is intended to solve these problems, and its purpose is to develop two types of complementary transistors that utilize two-dimensional electrons and two-dimensional hole gas and are suitable for complementary transistors that can operate at low power consumption and high speed. An object of the present invention is to provide a semiconductor device having a structure suitable for forming two transistors on the same substrate.
本発明の半導体装置は、
同一基板上に形成されたｎチャネルトランジスタと、ｎ
チャネルトランジスタを具え、該ｎチャネルトランジス
タは、少なくとも、不純物無添加のシリコン−ゲルマニ
ウム混晶層と、不純物無添加のシリコン層と、ｐ型シリ
コン層との３層の積層構造と、該積層構造上に設けられ
た第１高抵抗層と、該第１高抵抗層上に設けられた第１
ソース、ドレイン及びゲー）、電極を具え、前Ｒ’６
ｎチャネルトランジスタは、少なくともｎ型のンリコノ
ーゲルマニウム混晶層と、不純物無添加のシリコン−ゲ
ルマニウム混晶層と、不純物無添加のシリコン層との３
層の積層構造と、該積層構造上に設けられた第２高抵抗
層と、該第２高抵抗層上に設けられた第２ソース、ドレ
イン及びゲート電極を具え、
前記ｎチャネルトランジスタは、該不純物無添加のンリ
コンーゲルマニウム混晶層中に量子井戸を形成し、該量
子井戸は２次元ホールガスを、前記ｎチャネルトランジ
スタは、該不純物無添加のシリコン層中に量子井戸を形
成し、該量子井戸は２次元電子ガスをチャネルとし、
前記ｎチャネルトランジスタと前記のチャネルトランジ
スタのゲート電極下の構造は、シリコン及びシリコン−
ゲルマニウム混晶層が同一組成かつ同一の膜厚で、垂直
方向に変化しており、不純物密度のみが異なることを特
徴とする特〔実施例〕
以下、本発明について、実施例に基づき、詳細に説明す
る。A semiconductor device of the present invention includes an n-channel transistor formed on the same substrate, and an n-channel transistor formed on the same substrate.
The n-channel transistor includes a three-layer stacked structure including at least an impurity-free silicon-germanium mixed crystal layer, an impurity-free silicon layer, and a p-type silicon layer; a first high resistance layer provided on the first high resistance layer; and a first high resistance layer provided on the first high resistance layer.
source, drain and electrode), and the front R'6
The n-channel transistor includes at least three layers: an n-type silicon germanium mixed crystal layer, an impurity-free silicon-germanium mixed crystal layer, and an impurity-free silicon layer.
The n-channel transistor includes a stacked structure of layers, a second high resistance layer provided on the stacked structure, and second source, drain, and gate electrodes provided on the second high resistance layer. A quantum well is formed in an impurity-free silicon-germanium mixed crystal layer, the quantum well supplies a two-dimensional hole gas, and the n-channel transistor forms a quantum well in the impurity-free silicon layer; The quantum well uses a two-dimensional electron gas as a channel, and the structures under the gate electrodes of the n-channel transistor and the channel transistor are made of silicon and silicon-
A special feature in which the germanium mixed crystal layer has the same composition and the same thickness, changes in the vertical direction, and differs only in impurity density [Example] The present invention will be described in detail below based on Examples. explain.
第１図は本発明の半導体装置の略式断面図であり、Ａは
ｐチャネルトラフ９２２部、Ｂはｎチャネルトランジス
タ部である。FIG. 1 is a schematic cross-sectional view of the semiconductor device of the present invention, where A is a p-channel trough 922 portion and B is an n-channel transistor portion.
１はシリコン基板であり、高抵抗のものを用いているが
、トランジスタ間の素子分離を行なうならば高抵抗の必
要はない。２はｐチャネルとｎチャネルの分離領域であ
り、絶縁体を埋めこんでいる。８も絶縁体で層間絶縁瞑
である。３はシリコン−ゲルマニウム混晶のスペーサ層
で、１のＭｌｌＩｉＥ側から上方に向って、ゲルマニウ
ムの組成が増大するように作られており、例えば、ゲル
マニウムの組成が０から０．５まで変化する。Reference numeral 1 denotes a silicon substrate having high resistance, but if isolation between transistors is to be achieved, high resistance is not necessary. Reference numeral 2 denotes a p-channel and n-channel separation region, which is filled with an insulator. 8 is also an insulator and has interlayer insulation. 3 is a spacer layer of silicon-germanium mixed crystal, which is formed so that the germanium composition increases upward from the MllIiE side of 1; for example, the germanium composition changes from 0 to 0.5.
まず、ｎチャネルトランジスタについて説明する。４は
シリコン−ゲルマニウム混晶層で、５の不純物無添加の
シリコン層との界面近傍に２次元ホールガスが形成され
、チャネル領域となる。６はｐ型のシリコン層であり、
２次元ホールガスを形成するためには、少なくとも、上
記５．６．７の、３層の積層構造が必要である。７は高
抵抗層で１０のゲート電極とシ□ットキー接合を形成さ
せるためのものである。９はソース電極、１）はドレイ
ンｆｆｌ ｔｆｆｉである。１２．１３はイオン注入等
によって形成された高濃度のｐ型領域で、それぞれ、ソ
ース及びドレインである。First, the n-channel transistor will be explained. 4 is a silicon-germanium mixed crystal layer, and a two-dimensional hole gas is formed near the interface with the impurity-free silicon layer 5, forming a channel region. 6 is a p-type silicon layer;
In order to form a two-dimensional hole gas, at least a three-layer stacked structure as described in 5.6.7 above is required. 7 is a high resistance layer for forming a Schottky junction with the gate electrode 10; 9 is a source electrode, and 1) is a drain ffl tffi. 12 and 13 are highly doped p-type regions formed by ion implantation or the like, which are the source and drain, respectively.
次に、ｎチャネルトランジスタについて説明する。２０
はｎ型のシリコン−ゲルマニウム混晶層であり、１９は
不純物無添加のシリコン−ゲルマニウム混晶層、１８は
不純物無添加のシリコン層である。１９と２０の界面近
傍の２０のシリコン層中に２次元電子ガスが形成される
が、そのためには、少なくとも、１８．１９．２０の３
層の４ｊｆ層構造が必要である。１７は高抵抗層である
が、１８の不純物無添加のシリコン層と同じ材質でかま
わない。１５はゲート電ｔ！、１４、Ｌ、Ｓはそれぞれ
、ドレイン電極、ソース電極である。２１．２２はｎ型
の不純物をイオン注入等により導入したドレイ乙 ソー
スである。Next, the n-channel transistor will be explained. 20
is an n-type silicon-germanium mixed crystal layer, 19 is a silicon-germanium mixed crystal layer to which no impurities are added, and 18 is a silicon layer to which no impurities are added. A two-dimensional electron gas is formed in the silicon layer 20 near the interface between 19 and 20.
A 4jf layer structure of layers is required. Although 17 is a high resistance layer, it may be made of the same material as the impurity-free silicon layer 18. 15 is the gate electric t! , 14, L, and S are a drain electrode and a source electrode, respectively. 21 and 22 are drain sources into which n-type impurities are introduced by ion implantation or the like.
以上、本発明の半導体装置の構造について述べてきたが
、その動作を説明するため、第２図にポテンシャル図を
示す。第２図（Ａ）はｎチャネルトランジスタ、第２図
（Ｂ）はｎチャネルトランジスタの、ゲート電極下部の
ポテンシャル図である。横方向は深さ方向を現している
が、各層の厚さは、わかりやす（描いたもので、この図
とは異なっている。丸印で囲まれている部分にそれぞれ
２次元ホールガス、２次元電子ガスが存在する。The structure of the semiconductor device of the present invention has been described above, and a potential diagram is shown in FIG. 2 to explain its operation. FIG. 2(A) is a potential diagram of the lower part of the gate electrode of an n-channel transistor, and FIG. 2(B) is a potential diagram of the lower part of the gate electrode of the n-channel transistor. The horizontal direction represents the depth direction, but the thickness of each layer is easy to understand (this is a drawing and is different from this figure.The areas surrounded by circles are two-dimensional hole gas, two-dimensional hole gas, two-dimensional Dimensional electron gas exists.
まず（ａ）図について説明する。２１はゲート電極でｌ
１図の１０に相当する。以下、２２．２３．２４．２５
．２６．２７はそれぞれ、第１図の７．６．５．４．３
．１に相当している。このｎチャネルトランジスタは、
ａ ｔ ０）Ｇ ａ Ａ ｓ ／ ＡρｘＧａ＋ −ｘ
Ａｓ系の２次元電子ガスを利用したトランジスタと同様
に、バンドギャップの小さい半導体層中に、キャリアを
蓄積させるものである。従って、この図では、ホールが
不純物散乱の影響を受けずに高速で動作するｎチャネル
トランジスタとなる。First, Figure (a) will be explained. 21 is the gate electrode l
This corresponds to 10 in Figure 1. Below, 22.23.24.25
．． 26.27 are respectively 7.6.5.4.3 in Figure 1
．． It corresponds to 1. This n-channel transistor is
a t 0) G a As / AρxGa+ -x
Similar to transistors using As-based two-dimensional electron gas, carriers are accumulated in a semiconductor layer with a small band gap. Therefore, in this figure, the hole becomes an n-channel transistor that operates at high speed without being affected by impurity scattering.
次に（ｂ）図であるが、２８はゲート電極で第１図１５
に相当する。以下、２９．３０．３１．３２．３３．３
４はそれぞれ、第１図の１７．１８．１９．２０．３．
１に相当している。このｎチャネルトランジスタは、Ｇ
ａ Ａ ｓ ／ ＡρｘＧａ、−ｘＡｓ系のへテロ接
合と異なり、バンドギャップの広い半導体層中にキャリ
アを蓄積させるものである。従って、この図では、電子
が不純物散乱の影砦を受けずに高速で動作するｎチャネ
ルトランジスタとなる。Next, in FIG. 1B, 28 is a gate electrode.
corresponds to Below, 29.30.31.32.33.3
4 correspond to 17, 18, 19, 20, 3, etc. in FIG. 1, respectively.
It corresponds to 1. This n-channel transistor has G
Unlike the aAs/AρxGa, -xAs-based heterojunction, carriers are accumulated in a semiconductor layer with a wide bandgap. Therefore, in this figure, the transistor becomes an n-channel transistor in which electrons operate at high speed without being affected by impurity scattering.
相補型でトランジスタを動作させるためには、ｎチャネ
ルトランジスタ、ｎチャネルトランジスタともにノーマ
リ−オフでなければならない。また、相互コンダクタン
スの値もバランスがきれていることが要求される。この
ため、ｎチャネルトランジスタ、ｎチャネルトランジス
タともに、各層の厚さ、混晶の組成、不純物Ｏ１ｆは正
確に制御する必要があり、また、その解は種々あるが、
第２図のポテンシャルが実現されていることが必要であ
る。ゲート電極の材料もトランジスタのスレッンコルド
電圧を左右するパラメータである。本発明ではＰｔを用
いているが、Ｔ１等多くの材料が考えられるのは当然で
あり、ｐチャネル、ｎチャネル別々の材料にすることが
できるのも当然である。In order to operate the transistors in a complementary manner, both the n-channel transistor and the n-channel transistor must be normally off. It is also required that the mutual conductance values be well balanced. For this reason, it is necessary to accurately control the thickness of each layer, the composition of the mixed crystal, and the impurity O1f for both n-channel transistors and n-channel transistors, and there are various solutions.
It is necessary that the potential shown in Figure 2 be realized. The material of the gate electrode is also a parameter that affects the Threncord voltage of the transistor. Although Pt is used in the present invention, it is natural that many materials such as T1 can be considered, and that it is also possible to use different materials for p-channel and n-channel.
上述の如（、本発明の半導体装置によれば、ｐチャネル
トランジスタは２次元ホールガスを利用し、ｎチャネル
トランジスタは２次元電子ガスを利用するため、どちら
も大きな相互コンダクタンスを持つ。また、シリコン−
ゲルマニウム系に於いては、電子移動度とポール移動度
が比較的近い値をもつため、各層の膜厚、組成、不純物
密度を適切な値とすれば、ｐチャネルトランジスタとｎ
チャネルトランジスタの占を面積を等しくすることがで
きるため、相補型トランジスタとしての特徴を十分に生
かすことができる。すなわち、超低消費電力で高速動作
のトランジスタとして、超大規模集積回路に利用できる
。とくに、本発明の構造をとれば、ｐチャネルトランジ
スタ部とｎチャネルトランジスタ部の変調ドーピングに
対して、同時に選択ドーピングを行うことが可能であり
、ｎチャネル用とｎチャネル用の結晶成長は別々に行う
必要がない。As described above (according to the semiconductor device of the present invention, the p-channel transistor uses two-dimensional hole gas and the n-channel transistor uses two-dimensional electron gas, so both have large mutual conductance. −
In germanium-based materials, electron mobility and pole mobility have relatively similar values, so if the film thickness, composition, and impurity density of each layer are set to appropriate values, p-channel transistor and n
Since the areas of the channel transistors can be made equal, the characteristics as complementary transistors can be fully utilized. In other words, it can be used in ultra-large scale integrated circuits as a transistor with ultra-low power consumption and high-speed operation. In particular, with the structure of the present invention, it is possible to perform selective doping for the modulation doping of the p-channel transistor section and the n-channel transistor section at the same time, and the crystal growth for the n-channel and for the n-channel can be performed separately. There's no need to do it.
第１図は本発明の半導体装置の断面模式図で、Ａの部分
はｐチャネルトランジスタ、Ｂの部分はｎチャネルトラ
ンジスタを示す図。
第２図（ａ）、（ｂ）において、 同図（ａ）は、本発
明のｐチャネルトランジスタのゲート下部のポテンシャ
ル図。同図（ｂ）は、ｎチャネルトランジスタのゲート
下部のボテーンシャル図。
以 上
出馴人 セイコーエプソン株式会社
代理人 弁理士 最 上 務 他１名第１函
（α）
遅
（ｂ）
第Ｚ区FIG. 1 is a schematic cross-sectional view of a semiconductor device of the present invention, in which the part A shows a p-channel transistor and the part B shows an n-channel transistor. In FIGS. 2(a) and 2(b), FIG. 2(a) is a potential diagram below the gate of the p-channel transistor of the present invention. FIG. 6(b) is a vocative diagram of the lower part of the gate of the n-channel transistor. Those who are familiar with Seiko Epson Co., Ltd. Patent attorney Tsutomu Mogami and 1 other person Box 1 (α) Late (b) District Z
Claims (3)
とｎチャネルトランジスタを具え、 該ｐチャネルトランジスタは、少なくとも不純物無添加
のシリコン−ゲルマニウム混晶層と、不純物無添加のシ
リコン層と、ｐ型シリコン層との３層の積層構造と、該
積層構造上に設けられた第１高抵抗層と、該第１高抵抗
層上に設けられた第１ソース、ドレイン及びゲート電極
を具え、前記ｎチャネルトランジスタは、少なくともｎ
型のシリコン−ゲルマニウム混晶層と、不純物無添加の
シリコン−ゲルマニウム混晶層と、不純物無添加のシリ
コン層との３層の積層構造と、該積層構造上に設けられ
た第２高抵抗層と、総第２高抵抗層上に設けられた第２
ソース、ドレイン及びゲート電極を具え、 前記ｐチャネルトランジスタは、該不純物無添加のシリ
コン−ゲルマニウム混晶層中に量子井戸を形成し、該量
子井戸は２次元ホールガスを、前記ｎチャネルトランジ
スタは、該不純物無添加のシリコン層中に量子井戸を形
成し、該量子井戸は２次元電子ガスをチャネルとし、 前記ｐチャネルトランジスタと前記のチャネルトランジ
スタのゲート電極下の構造は、シリコン及びシリコン−
ゲルマニウム混晶層が、同一組成かつ同一の膜厚で、垂
直方向に変化しており、不純物密度のみが異なることを
特徴とする半導体装置。(1) A p-channel transistor and an n-channel transistor formed on the same substrate, and the p-channel transistor includes at least an impurity-free silicon-germanium mixed crystal layer, an impurity-free silicon layer, and a p-type silicon a first high resistance layer provided on the multilayer structure, and first source, drain, and gate electrodes provided on the first high resistance layer, and the n-channel The transistor has at least n
A three-layer stacked structure of a molded silicon-germanium mixed crystal layer, an impurity-free silicon-germanium mixed crystal layer, and an impurity-free silicon layer, and a second high-resistance layer provided on the stacked structure. and a second layer provided on the total second high resistance layer.
The p-channel transistor has a source, a drain, and a gate electrode, and the p-channel transistor has a quantum well formed in the undoped silicon-germanium mixed crystal layer, and the quantum well carries a two-dimensional hole gas. A quantum well is formed in the impurity-free silicon layer, the quantum well uses a two-dimensional electron gas as a channel, and the structures under the gate electrodes of the p-channel transistor and the channel transistor are made of silicon and silicon-
A semiconductor device characterized in that germanium mixed crystal layers have the same composition and the same thickness, vary in the vertical direction, and differ only in impurity density.
タのチャネル領域が、選択変調ドーピングにより形成さ
れることを特徴とする特許請求第１項記載の半導体装置
。(2) The semiconductor device according to claim 1, wherein the channel regions of the p-channel transistor and the n-channel transistor are formed by selective modulation doping.
層をスペーサ層として具え、該スペーサ層はゲルマニウ
ムの組成が基板から素子側に向って大きくなることを特
徴とする特許請求の範囲第２項記載の半導体装置。(3) A silicon-germanium mixed crystal layer is provided as a spacer layer on a silicon substrate, and the spacer layer has a germanium composition that increases from the substrate toward the element side. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14559587A JPS63308966A (en) | 1987-06-11 | 1987-06-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14559587A JPS63308966A (en) | 1987-06-11 | 1987-06-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63308966A true JPS63308966A (en) | 1988-12-16 |
Family
ID=15388705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14559587A Pending JPS63308966A (en) | 1987-06-11 | 1987-06-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63308966A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5266813A (en) * | 1992-01-24 | 1993-11-30 | International Business Machines Corporation | Isolation technique for silicon germanium devices |
| US5534713A (en) * | 1994-05-20 | 1996-07-09 | International Business Machines Corporation | Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers |
| US5561302A (en) * | 1994-09-26 | 1996-10-01 | Motorola, Inc. | Enhanced mobility MOSFET device and method |
| US6674100B2 (en) | 1996-09-17 | 2004-01-06 | Matsushita Electric Industrial Co., Ltd. | SiGeC-based CMOSFET with separate heterojunctions |
-
1987
- 1987-06-11 JP JP14559587A patent/JPS63308966A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5266813A (en) * | 1992-01-24 | 1993-11-30 | International Business Machines Corporation | Isolation technique for silicon germanium devices |
| US5534713A (en) * | 1994-05-20 | 1996-07-09 | International Business Machines Corporation | Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers |
| US5561302A (en) * | 1994-09-26 | 1996-10-01 | Motorola, Inc. | Enhanced mobility MOSFET device and method |
| US6674100B2 (en) | 1996-09-17 | 2004-01-06 | Matsushita Electric Industrial Co., Ltd. | SiGeC-based CMOSFET with separate heterojunctions |
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