JPS63308653A - Block-in system - Google Patents

Abstract

PURPOSE:To use the memory of a port size different from a microprocessor by executing a dynamic bus sizing and also changing over the update sequence of an access address according to the port size of a memory. CONSTITUTION:The system changes over the update sequence of the access address of a ROM 2 according to the port size of the ROM 2 and executes a dynamic bus sizing to shift the data on a data bus 3 according to the port size of the ROM 2. The system transfers beforehand prescribed block data with constant length from the ROM 2 to a cache memory 4 in a microprocessor 1. Thus, since the dynamic bus sizing is executed, the ROM of a port size different from the microprocessor can be used. And, since the update sequence of the access address is change over, the necessary part of data can be constantly accessed in advance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention is a block-in method for a data processor having a cache memory within a microprocessor, in which data is transferred from a device such as a memory having a port size different from that of the microprocessor via a data bus. In order to transfer data to the cache memory using dynamic bus sizing, the data on the data bus is shifted and taken in according to the port size, and when block-in access is performed, the access address is changed according to the port size. By switching the update order of the microprocessor, it is possible to use a device with a port size different from the microprocessor, and the data is always updated regardless of the port size and even if the data to be obtained exists across word boundaries. The necessary part of the file is accessed first.

(Industrial Application Field) The present invention relates to a block-in method, and particularly to a block-in method from a device such as a memory to a cache memory in a data processor having a cache memory within a microprocessor.

In recent years, there has been a demand for smaller and faster data processors. Therefore, the system configuration of the data processor is
It is desirable to have flexibility so that miniaturization and high speed can be achieved.

[Conventional technology]

FIG. 14 shows the configuration of a conventional data processor. The data processor generally includes a microprocessor 51, a read only memory (ROM) 52, a random access memory (RAM) 53, a peripheral circuit 54, an input/output control circuit 55, and a disk 56. The input/output υ1tl11 circuit 55 takes out data from a predetermined area on the disk 56 in response to a command from the microprocessor 51, for example. Microbrosse IJ-51, ROM52, RAM53
, peripheral circuit 54, and input/output control circuit 55 are connected by a bus 58, respectively.

When the power is turned on or immediately after a system reset, the ROM52
Using the program stored in the microprocessor 51, initial diagnosis is performed to determine whether the data in the RAM 53 is correct or whether it operates correctly, or whether the microprocessor 51 itself can correctly execute instructions. Perform a diagnosis. However, for example, if the RAM 53 has a capacity of about 2 Mbytes, it is necessary to diagnose whether or not the RAM 53 operates correctly by executing each instruction of the program in the ROM 52 and writing and reading data to and from the RAM 53 accordingly. If this is done, the diagnosis will take too much time due to the access time of the ROM 52 and the like.

Therefore, the microprocessor 51 has a built-in cache memory 59 that copies and stores a portion of the program in the ROM 52. The capacity of cache memory 59, which is a high-speed buffer memory, is smaller than that of RAM 53. This allows instructions of the program in the ROM 52 to be transferred to the cache memory 5 in the microprocessor 51.
The diagnosis time can be shortened. This is because the access time of ROM 52 is not included in the diagnostic time and the use of bus 58 is also minimized.

FIG. 15 is a diagram showing control by the ROM 52 after power is turned on. In addition to the initial diagnosis program, the ROM 52 also stores an initialization program and an IPL program for performing initial II program loading (['L). After the power is turned on, the registers in the data processor are initialized under ti11611 by the program in the ROM 52. Next, the initial diagnosis program in the ROM 52 causes the microprocessor 51, peripheral circuit 54, and R
Initial diagnosis is performed on the AM53 and the input/output 1IJ111 circuit 55, and further, IPL is performed using the IPL program in the ROM52.

[Problem that the invention seeks to solve]

In a conventional data processor, a microprocessor 51
The port size of each device connected by bus 58 is 1.
Designed to be fixed in size.

For this reason, for example, if the port size of the RAM 53 is 8 bits wide, the port size of the ROM 52 must also be 8 bits wide, otherwise the instructions of the program in the ROM 52 cannot be transferred to the cache memory 59 in the microprocessor 51 and executed. Can not.

Generally, the capacity of the ROM 52 is smaller than that of the RAM 53, for example, about 1 kbyte. Therefore, 8
When using a bit ROM@ROM52, there is no problem if the port size is the same 8-bit width, but if the port size is 32-bit wide, for example, this 8-bit RO
It is necessary to configure the ROM 52 using four M's. In other words, the capacity of the ROM 52 is the above 8-bit ROM.
lfll (about 1kbyte) is sufficient, but
In this case, four 8-bit ROMs must be used just to accommodate the 32-bit wide port size. As a result, if four 8-bit ROMs are used for a 32-bit wide port size, approximately 3 kbytes
There was a problem that e was redundant and the ROM usage efficiency was poor. In addition, since a ROM with a capacity that is not actually required is provided, especially in the case of data processors using very large scale integrated circuits (VLSI), there is a problem that the ROM occupies a large area, resulting in a decrease in the degree of integration. Ta.

(Means for Solving the Problems) The block-in method of the present invention provides access control of the memory device according to the port size of the memory device in a data processor consisting of a memory device and a microprocessor.
Dynamic bus sizing is performed in which the address update order is switched and the data on the data bus is shifted according to the port size of the memory device, and a predetermined block of data of a certain length is transferred from the memory device to the cache in the microprocessor. Transfer to memory.

[Effect]

The block-in scheme of the present invention allows the use of memory devices with different port sizes than the microprocessor to provide dynamic bus sizing. Furthermore, since the order of updating the access contention addresses of the memory device is changed according to the port size of the memory device, it is possible to always access the necessary part of the data first, regardless of the port size.

〔Example〕

FIG. 1 shows the configuration of a data processor to which the block-in method according to the present invention can be applied. In the figure, the same components as those in FIG. 14 are denoted by the same reference numerals, and the explanation thereof will be omitted.

The microprocessor 1 has a cache memory 4 therein, and is connected to a RO-M 2 and the like via a bus 3.

First, in the block-in method of the present invention, the block-in method
Each embodiment of the update order of the access address of the ROM2 which is changed according to the port size of the ROM2 when performing an in-access will be described. For convenience of explanation, the port size of microprocessor 1 is 32 bits wide;
It is assumed that one block of access addresses has the configuration shown in FIG. In Fig. 2, rOJ, rN,...

rFJ each indicates a byte address.

A first example of the access address update order will be described. It is assumed that the port size of ROM 2 is 8 bits wide, and that data straddles word boundaries. In FIG. 3.4, the byte address of the data word to be accessed is indicated by diagonal lines. In this embodiment, first, one byte of the specified byte address is read from ROM2, and if there is data in the word after this specified byte in the word where this specified byte exists, it is read up to the first byte of the word size, and then this byte is read. If there is data in the word before the specified byte in the word where the specified byte exists, it is read from the most significant byte in the word, the bytes in the next word are read in order from the most significant byte, and the most significant byte of the block is accessed. If not, access each byte including the word where the most significant byte of this block exists and up to the word before the word where the specified byte exists.

Therefore, in the case of FIG. 3, the access addresses r7J, r
4J, r5J, r6J, rBJ, r9J, rAJ, rB
It is updated in the order of J, rcJ, . . . , r2J, r3J. Similarly, in the case of FIG. 4, the access addresses are r5J, r6J, r7J.

r4J, rBJ, r9J, rAJ, rBJ, rcJ, ・
..., r2J, r3J are updated in this order.

A second example of the access address update order will be described. In this embodiment as well, the port size of the ROM 2 and the existence of data are the same as those described in the first embodiment. In this embodiment, first, one byte of the specified byte address is read from ROM2, and if there is data in the word after this specified byte in the word where the specified byte exists, it is read up to the lowest byte in the word, and then the specified byte is read. If there is data in the word before this specified byte in the word where the byte exists, it is read from the most significant byte in the word.
It is the same as the example. However, in this embodiment, 1 of the byte address obtained by adding "4" to the next specified byte address.
The byte was read from ROM2, and this "4" was added to the byte address, which was sequentially incremented using a wrap-around method in which only the lower two bits changed and no carry was allowed for the third bit, and then this "4" was added. Read each byte in the word that contains one byte of the byte address (
In other words, read the byte after and the byte before the byte at the byte address to which "4" has been added), and read from ROM2 the byte at the byte address to which "4" has been added and the byte address to which "4" has been added. , this byte address with "4" added to it is sequentially incremented in a wrap-around manner, and each byte in the word where 1 byte of this byte address with "4" added is present is read, and the following instructions are specified in the same way. Access each byte up to the word before the word in which the byte resides.

Therefore, in the case of Figure 3, the access address is r7J,
r4J, r5J, r6J, rBJ,
rBJ, r9J, rAJ, rFJ, ..., rlJ,
Updated in r2J order. Similarly, in the case of FIG. 4, the access addresses are r5J, r6J, r7J.

r4J, r9J, rAJ, rBJ, rBJ, rDJ, ・
..., r3J, rOJ are updated in this order.

A third example of the access address update order will be described. In this embodiment as well, the port size of the ROM 2 and the existence of data are the same as those described in the first embodiment. In this embodiment, first, one byte at a designated byte address is read from the ROM 2, and thereafter each byte in the block is read by sequentially incrementing the byte address.

Therefore, in the case of Figure 3, the access address is r7J,
rBJ, r9J, rAJ, rBJ, rCJ,..., r
It is updated in the order of 5J and r6J. Similarly, in the case of Figure 4, the access addresses are r5J, r6J, r7J.
, rBJ, r9J, rAJ, rBJ, rcJ,...
They are updated in the order of r3J and r4J.

Note that the byte address of the data to be accessed is the fifth byte address.
As shown in the figure, if the access address does not straddle a word boundary, the access address is rAJ, r5J, r6J, r7J, rBJ, r9J in any of the first to third embodiments.
, rAJ, rBJ.

They are updated in the order of "C", . . . , r2J, r3J.

Next, a fourth example of the update order of access addresses will be described. It is assumed that the port size of ROM 2 is 16 bits wide, and data straddles word boundaries. In FIGS. 6 and 7, byte addresses of data words to be accessed are indicated by diagonal lines. In this embodiment, if one byte of the specified byte address exists in the upper two bytes of the word in which the byte exists, first read the upper two bytes, then read the lower two bytes, and if the byte exists in the lower two bytes of the word. For example, the lower 2 bytes are read, then the upper 2 bytes are read, and thereafter the upper 2 bytes and lower 2 bytes in each word are sequentially accessed up to the word before the word in which the specified byte exists.

Therefore, in the case of FIG. 6, the access addresses are r6.7J, r4, and 5J in 2-byte units.

r8.9J, rA, BJ, rC, DJ,...
It is updated in the order of "2°3". Similarly, in the case of FIG. 7, the access address is r4 in 2-byte units.
．． 5J, r6.7J, r8.9J, rA.

They are updated in the order of BJ, rc, DJ, ..., r2.3J.

A fifth example of the access address update order will be described. In this embodiment as well, the port size of the ROM 2 and the existence of data are the same as those described in the fourth embodiment. In this embodiment, first, if one byte of the specified byte address exists in the upper two bytes of the word in which that byte exists, the upper two bytes
The steps from reading the byte to reading the lower 2 bytes and reading the lower 2 bytes and then reading the upper 2 bytes if the word exists in the lower 2 bytes are the same as in the fourth embodiment.

However, in this embodiment, the next specified byte address is “4”.
Read the upper or lower 2 bytes that include 1 byte of the byte address to which "4" has been added, then increment the byte address to which "4" has been added sequentially in a wrap-around manner to obtain the byte address to which "4" has been added. The lower or upper 2 byte of the byte address added with this "4" is not included in the word where 1 byte exists.
Read the byte, read the upper or lower 2 bytes that include 1 byte of the byte address that is the byte address that is the result of adding this “4”, and then add this “4”.
The byte address obtained by adding ``4'' is sequentially incremented in a wrap-around manner, and within the word where 1 byte of the byte address obtained by adding ``4'' is included, 1 byte of the byte address obtained by adding ``4'' is included. The lower or upper 2 bytes that do not exist are read, and each 2 byte is accessed in the same manner up to the word before the word where the specified byte exists.

Therefore, in the case of FIG. 6, the access addresses are r6, 7J, and r4.5J in 2-byte units.

They are updated in the order of rA, BJ, r8, 9J, rE, FJ, . . . "0°1". Similarly, in the case of Figure 7,
The access address is r4.5J in 2-byte units.
, r6.7J, r8.9J, FA.

It is updated in the order of BJ, rc, DJ, . . . , r2.3J.

A sixth embodiment of the access address update order will be described. In this embodiment as well, the port size of the ROM 2 and the existence of data are the same as those described in the fourth embodiment. In this embodiment, first the upper or )-order two bytes included in one byte of the designated byte address are read, and thereafter each two bytes in the block are read by sequentially adding "2" to the byte address.

Therefore, in the case of FIG. 6, the access addresses are r6.7J, r8, and 9J in 2-byte units.

They are updated in the order of rA, BJ, rC, DJ, . . . , r4.5J. Similarly, in the case of FIG. 7, the access addresses are r4.5J, r6.
．． 7J, r8.9J, rA, BJ, rC.

It is updated in the order of DJ, . . . , r2.3J.

Note that the byte address of the data to be accessed is the 8th byte address.
As shown in the figure, if the access address does not straddle a word boundary, the access address is r4.5J, r6.7J in 2-byte units in any of the fourth to sixth embodiments.
, r8.9J, rA, BJ, rC, DJ, ..., r
2. Updated in the order of 3J.

As is clear from the above description, the 1.4 embodiments basically use the same first update order, although there are differences due to different port sizes. Similarly, the second.
The fifth embodiment basically uses the same second update order, and the third and sixth embodiments basically use the same third update order.

Next, a seventh embodiment of the access address update order will be described. The port size of ROM2 is 32 bits wide, and FIG. 9.10 shows a case where data straddles a word boundary, and FIG. 11 shows a case where data does not straddle a word boundary. In Figures 9-11, the byte address of the data word to be accessed is indicated by diagonal lines. In this embodiment, first, a word containing one byte of a specified byte address is read, and
Thereafter, each word is accessed up to the word before the word containing the specified byte. Therefore, no matter which of the first to third update orders are used, the update order is the same. In other words, in the case of Figures 9 to 11, the access addresses are all expressed in word units as "4°5.6.7J, r8.9.A,
BJ, rc, D.

Updated in the order of E, FJ, ro, 1.2.3J.

Next, an embodiment of the configuration of the main parts of the microprocessor 1 will be described with reference to FIG. 12. FIG. 12 shows the arithmetic control section 11, storage control section 12, and input/output control section 13 within the microprocessor 1. The storage-control unit 12 generally includes an instruction cache memory 14, an operand cache memory 15, an instruction translation lookaside buffer (TLB) 16, and an operand TLB 17.
It consists of a circuit including. Instruction cache memory 14 and operand cache memory 15 constitute cache memory 4. Note that a single cache memory can be divided into instruction cache memory and operand cache memory.
It may also be used as memory. The input/output control section 13 generally includes a shifter matrix circuit 18, a dynamic bus sizing circuit 19, and an address incrementer 2.
It consists of a circuit containing 0.

For example, assume that there is an instruction from the arithmetic control unit 11 to add data AA stored in area A in the ROM 2 and data BB stored in area B, and to store the sum in area B. In this case, the operand TLB 17 determines whether data AA and BB are stored in the operand cache memory 15. If the data AA and 8B are stored in the cache memory 15, the operand cache memory 15 is accessed and the data AA and BB are added together, and the sum is added to the operand cache memory 15 without directly accessing ROM2, which requires a long access time. The data is stored in the cache memory 15. For example, when accessing addresses O to 3, if addresses O to 3 of ROM2 are system-only areas, addresses O to 3 are access prohibited areas, and addresses O to 3 are accessed, for example, to addresses 1000 to 10.
03 and actually access addresses 1000 to 1003. In other words, addresses O to 3 in this case are essentially virtual addresses, and address 100
0 to 1003 are real addresses. Operand TLB1
7 performs such address conversion as necessary.

Instruction cache memory 14 is the same as operand cache memory 15 except that it stores instructions rather than data, and similarly instruction TLB 16 is the same as operand TLB 17.

Therefore, instruction cache memory 14 and instruction TLB1
6 will be omitted.

The desired data (or instructions) are stored in the cache memory 15 (
or 14), a part of the ROM 2 containing this desired data is copied and stored in the cache memory 15 (or 14). RO this desired data
When fetching M2, the dynamic bus sizing circuit 19 outputs a byte mark, and the address incrementer 20 outputs the address to be accessed. Even if the desired data is 4 bytes, access is performed in units of 16 byte blocks as shown in FIG. In this way, one block of data is RO
A cycle in which data is fetched from M2 and this one block of data is stored (blocked in) in the operand cache memory 15 via the bus 3 is called a block-in cycle. When performing block-in to the operand cache memory 15, the dynamic bus sizing circuit 19 determines the port size of the ROM 2 from the port size signal, and uses the address incrementer 20.
indicates the next address to occur. This causes the address incrementer 20 to dynamically
The access address is generated under the control of the bus sizing circuit 19 in accordance with the port size and in an update order selected from the first to third update orders.

The port size signal is, for example, a 2-bit signal, and R
Represents the OM2 port size. port size signal 2
The bits are r00J and roll respectively.

If it is "10", the port size is 32 bits wide.

Assuming 16 bit width and 8 bit width, 2 bits are “11
”, it will be reserved.

Depending on the port size of the ROM 2, the used bits of the data bus in the bus 3 (valid byte positions on the data bus) differ. Therefore, it is necessary to appropriately switch the connection to the data bus depending on the port size. The shifter matrix circuit 18 responds to the control structure output from the dynamic bus sizing circuit 19 in response to a signal indicating the data length from the dedicated controller 11 and a predetermined lower bit of the access address from TLBl 7 or 16. It essentially switches the connection to the data bus in response, and is a type of data shifter that accommodates differences in connection to the data bus due to different port sizes.

As a result, the read data from ROM2 on the data bus is shifted appropriately according to the port size by the shifter matrix circuit 18, and then transferred to the cache memory 1.
4 or 15. Also, cache memory 14
Alternatively, the write data from 15 is appropriately shifted by the shifter matrix circuit 18 according to the port size and is supplied to the ROM 2 via the data bus.

In addition, in FIG. 12, a data bus and an address bus.

It is assumed that the port size signal line and the byte mark signal line are each included in the bus 3 in FIG.

Next, an embodiment of the input/output control section 13 in FIG. 12 will be described with reference to FIG. 13. In FIG. 13, the shifter matrix circuit 18 includes a matrix control circuit 25, selectors 26, 27, and latch circuits 28, 29. The dynamic bus sizing circuit 19
It consists of a mark generation circuit 30, a byte mark update circuit 31, a multiplexer 32, and a latch circuit 33.

Address incrementer 20 is connected to multiplexer 34
, an adder circuit 35 , and a latch circuit 36 .

The byte mark generation circuit 30 receives a 2-bit signal indicating the data length from the performance frame control circuit 11 and TLB16 or 1.
It is supplied with the lower 2 bits of the access address from 7 and generates and outputs a 4-bit byte mark indicating the valid byte position on the data bus. This byte mark is supplied to a byte mark update circuit 31 and a matrix control circuit 25. The matrix control circuit 25 is
Read/write signals are also supplied from a control circuit within the storage control section 12, which is not shown in FIG. A control circuit within the storage control unit 12 includes a cache memory 14.
15 and TLB16.17, it is a circuit that controls read (read) or write (
write) operation. Therefore, the matrix control circuit 25 selects the selector 26 in response to the byte mark and read/write signals from the byte mark generation circuit 30.
．． 27, read data or write data is shifted according to the port size.

The byte mark update circuit 31 determines whether the data spans a word boundary based on the byte mark and the signal indicating the data length from the byte mark generation circuit 30, and updates the byte mark. This updated byte mark is provided to multiplexer 32. The multiplexer 32 selects a byte when accessing the first byte when the port size is 8 bits wide (when accessing the first two bytes when the port size is 16 bits wide, and when accessing the first word when the port size is 32 bits wide).・Mark generation circuit 3
Selectively outputs byte marks starting from 0, and from then on, bytes/marks are output.
The updated byte mark from the mark update circuit 31 is selectively output. The byte mark from the multiplexer 32 is output from the input/output control section 13 via the wrap circuit 33.

Note that the byte mark update circuit 31 supplies the adder circuit 35 with a control signal instructing one access address update order among the first to third update orders, based on the boat size signal.

The adder circuit 35 sequentially adds a value according to the control signal from the byte mark update circuit 31 to the output lower 4-bit address of the multiplexer 34.

For example, in the case of the data in FIG. 3, if the first update order is selected, the adder circuit 35 increments the byte addresses in a wrap-around manner when byte address "7" is accessed, and increments the byte addresses r4J, r5J.
, r6J, 111 all is performed so that the byte addresses after byte address "7" are sequentially incremented and output. In the case of the data in Figure 3, the second
If the update order is selected, when the byte address "7" is accessed, the Korean circuit 35 sequentially increments the byte address in a wrap-around manner and outputs the byte addresses r4J, r5J, and r6J, and then outputs the byte address "7". It is controlled to repeat the operation of adding "4" to "4" and incrementing the byte address (rBJ) to which "4" has been added in a wrap-around manner to output byte addresses r8J, r9J, and rAJ. Furthermore, if the third update order is selected in the case of the data in FIG. 3, when the adder circuit 35 accesses byte address "7", it sequentially increments the byte addresses and writes byte addresses r8J, r9J, rAJ', . . .・It is controlled to output.

The multiplexer 34 is supplied with the lower 4 bits of the access address from the storage control unit 12 and the 4-bit output of the adder circuit 35. This multiplexer 34 is used when accessing the first byte when the port size is 8 bits wide (when accessing the first 2 bytes when the port size is 16 bits wide, and when accessing the first word when the port size is 32 bits wide). The lower 4 bits of the access address from the storage control unit 12 are selectively output, and thereafter the 4-bit output of the adder circuit 35 is selectively output.

The 4-bit output of the adder circuit 35 and the upper 28 bits of the access address from the storage controller 12 are output from the input/output controller 13 as a 32-bit address via the latch circuit 36, respectively. Note that the 4-bit output of the adder circuit 35 is stored in the cache memory 14.15 in the storage control unit 12.
It is also supplied to the cache memories 14 and 15 and used during write operations to these cache memories 14 and 15.

In the above explanation, the present invention is applied to block input from ROM 2 to cache memory 4, but the present invention is not limited to this, and can also be applied to block input from other devices such as memory. Needless to say, it is.

〔Effect of the invention〕

According to the present invention, since dynamic bus sizing is used, data from a device such as a memory having a port size different from that of the microprocessor in the data processor is transferred to the cache memory in the microprocessor via the data bus ( block-in) is now possible,
Furthermore, when performing a block φ-in access, the update order of access addresses is switched according to the port size of the device, so devices with port sizes different from the microprocessor can be used within the data processor.1. Regardless of the port size and even if the data to be obtained exists across word boundaries, the necessary part of the data can always be accessed first.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a data processor to which an embodiment of the block-in method according to the present invention can be applied. FIG. 2 is a diagram showing the configuration of one block of access addresses. The first in the update order of the access address
- Figures 6 to 8 are diagrams for explaining the access address update order in the fourth to sixth embodiments, and Figures 9 to 11 are diagrams for explaining the access address update order, respectively. A diagram for explaining the seventh embodiment of the sequence, FIG. 12 is a block diagram showing an embodiment of the main part of the microprocessor, and FIG. 13 shows an embodiment of the input/output control section in FIG. 12. Block diagram: Figure 14 is a block diagram showing the configuration of a conventional data processor; Figure 15 is an 11Jt block diagram using the ROM in the data processor.
FIG. In FIGS. 1, 12, and 13, 1 is a microprocessor, and 2 is a ROM. 3 is a bus, 4 is a cache memory, 11 is a sieve control phloem, 12 is a storage control section, 13 is an input/output control section 11, 14 is an instruction cache memory, 15 is an operand cache memory, 16 is an instruction TL
B. 17 is the operand TLB. 18 is a shifter matrix circuit, 19 is a dynamic bus sizing circuit, 20 is an address incrementer, 25 is a matrix control circuit, 26.27 is a selector, 28.29.33.36 is a latch circuit, 30 is a byte
31 is a byte mark update circuit; 32, 34 is a multiplexer; 35 is an adder circuit; 53 is a RAM. 54 is a peripheral circuit, 55 is an input/output & IJ circuit, and 56 is a disk. Figure i shows the *mH structure of the 2nd address of 7b, 7th address.
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Claims (8)

[Claims] (1) In a block-in method in a data processor consisting of a memory device and a microprocessor having an internal cache memory that are connected to each other by a data bus, the access address of the memory device is determined according to the port size of the memory device. Dynamic bus sizing is performed in which the data on the data bus is shifted according to the port size, and a predetermined block of data of a certain length is transferred from the memory device to the cache memory. The block-in method is characterized by: (2) If the port size of the microprocessor is 32 bits wide and the port size of the memory device is 8 bits wide, one block of data to be transferred to the cache memory consists of 16 bytes; When accessing a data word consisting of 4 bytes within the memory device, the order of updating the access address is to first read one byte at the specified byte address from the memory device, and then read the byte after this specified byte in the word in which this specified byte exists. If there is data in the word, it is read up to the least significant byte in the word, and if there is data in the word before this specified byte in the word where this specified byte exists, it is read from the most significant byte in the word, and this specified byte is read. Read the data in the word next to the word where the block exists, starting from the most significant byte, and if the most significant byte of the block is not accessed, read up to the word before the word where the specified byte exists, including the word where the most significant byte of this block exists. A block-in method according to claim 1, characterized in that each byte is switched to be read in sequence. (3) If the port size of the microprocessor is 32 bits wide and the port size of the memory device is 8 bits wide, one block of data to be transferred to the cache memory consists of 16 bytes; When accessing a data word consisting of 4 bytes within the memory device, the order of updating the access address is to first read one byte at the specified byte address from the memory device, and then read the byte after this specified byte in the word in which this specified byte exists. If there is data in the word, it is read up to the least significant byte in the word, and if there is data in the word before this specified byte in the word where this specified byte exists, it is read from the most significant byte in the word, and the specified byte address is read. Read one byte of the byte address obtained by adding "4" to the byte address, and if there is data in the word after the byte of the byte address to which this "4" is added, read it to the lowest byte in the word, and read this "4"
If there is data in the word before the byte at the byte address that has been added, read it from the most significant byte in the word,
The data in the word containing the byte of the byte address obtained by adding "4" to the byte address obtained by adding "4" is read in the same order, and the process is repeated to the word before the word containing the specified byte. A block-in method according to claim 1, characterized in that: (4) If the port size of the microprocessor is 32 bits wide and the port size of the memory device is 8 bits wide, one block of data to be transferred to the cache or memory consists of 16 bytes; When accessing a data word consisting of 4 bytes, the access address is updated in the following order: First, one byte of the specified byte address is read from the memory device, and then the specified byte address is sequentially incremented to read the previous byte of the specified byte. A block-in method according to claim 1, characterized in that the block-in method switches to sequentially read each byte up to a byte. (5) If the port size of the microprocessor is 32 bits wide and the port size of the memory device is 16 bits wide, one block of data to be transferred to the cache memory consists of 16 bytes; When accessing a data word consisting of 4 bytes, the access address is updated in the following order: first, if a byte of the specified byte address exists in the upper 2 bytes of the word in which that byte exists, read the upper 2 bytes; Read the lower 2 bytes from the memory device, if it exists in the lower 2 bytes of the word, read the lower 2 bytes, then read the upper 2 bytes, and read the data in the word next to the word in which this specified byte exists. Read bytes in order, and if the most significant 2 bytes of the block are not accessed, switch to read each 2 bytes in order, including the word in which the most significant 2 bytes of this block exist, up to the word before the word in which the specified byte exists. A block-in method according to claim 1, characterized in that: (6) If the port size of the microprocessor is 32 bits wide and the port size of the memory device is 16 bits wide, one block of data to be transferred to the cache memory is composed of 16 bytes; When accessing a data word consisting of 4 bytes, the access address is updated in the following order: first, if a byte of the specified byte address exists in the upper 2 bytes of the word in which that byte exists, read the upper 2 bytes; Read the lower 2 bytes from the memory device, and if it exists in the lower 2 bytes of the word, read the lower 2 bytes, then read the upper 2 bytes, and the 1 byte at the byte address obtained by adding "4" to the specified byte address is If the byte exists in the upper 2 bytes of the word, read the upper 2 bytes, then read the lower 2 bytes. If the byte exists in the lower 2 bytes of the word, read the lower 2 bytes, then read the upper 2 bytes, and then "
The data in the word containing the byte of the byte address obtained by adding "4" to the byte address obtained by adding "4" is read in the same order until the word before the word containing the specified byte is switched. A block-in method according to claim 1, characterized in that: (7) If the port size of the microprocessor is 32 bits wide and the port size of the memory device is 16 bits wide, one block of data to be transferred to the cache memory consists of 16 bytes; When accessing a data word consisting of 4 bytes, the access address is updated in the following order: First, if a byte of the specified byte address exists in the upper 2 bytes of the word in which that byte exists, the upper 2 bytes are moved to the memory. If it exists in the lower 2 bytes of the read word from the device, read the lower 2 bytes, and then sequentially add "2" to the byte address of the upper or lower 2 bytes included in the specified byte to determine the upper or lower address of the specified byte. 2. The block-in method according to claim 1, wherein the block-in method is switched to sequentially read each 2 bytes up to the 2 bytes before the 2 bytes. (8) If the port size of the microprocessor and the port size of the memory device are each 32 bits wide, one block of data to be transferred to the cache memory consists of 16 bytes, and 4 bytes in that one block When accessing a data word, the update order of the access address is changed so that the word containing one byte of the specified byte address is read first, and then the next word is read sequentially up to the word before the word containing the specified byte. A block-in method according to claim 1, characterized in that: