JPS6329343B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal capture circuit that captures a predetermined signal from a video signal in a PCM player or the like.

As a recording/playback device for analog signals such as acoustic signals, the analog signal to be recorded is instantaneously converted into a digital signal corresponding to the instantaneous amplitude, recorded in the form of this digital signal, and then converted back into the digital signal during playback. There are PCM recording and playback devices that convert signals into analog signals and output them. In this case, the magnetic tape of the VTR is used as the recording medium, taking advantage of its broadband characteristics, and in this case, the VTR's own control system is also used. Note that in this case, the signal waveform is converted into a signal pattern compliant with the NTSC system, for example.

When assuming a two-head helical scan type consumer VTR as a VTR, it is expected that there will be many head switching timing problems and errors near the vertical synchronization signal, so data is generally stored in one horizontal period (hereinafter simply referred to as 1H). ) is taken as one frame, and data is entered in the horizontal period excluding the horizontal period near the vertical synchronization signal. For example, the number of horizontal periods in one vertical period
Of 262.5, data is inserted into 245H excluding the horizontal signal period near the vertical synchronization signal, and in one frame where one horizontal period is one frame, in addition to six words of acoustic data, correction data, error data, etc. Detection data and a cue signal are added. For this reason, a method is used in which the digital signal output by the analog-to-digital conversion circuit is temporarily stored in a storage device, and the stored signal is read out at a period different from the stored period.

As described above, data is input into the 245 horizontal periods, and control signals for controlling various types of equipment are input into the other horizontal periods. For example, a control signal is input from the vertical synchronization signal into the first horizontal period, and then data is input from the second to the 246th horizontal period.

Here, since the control signal and the data have the same pattern structure, a specific fixed pattern is used as the control signal, and the control signal is obtained by detecting the pattern. However, sometimes the data pattern is the same as the fixed pattern above, and in that case, the data of the data frame may be mistaken for the control signal, for example, the P, Q correction code, which is one of the control signals. The presence or absence of data is falsely detected, resulting in a failure in which erroneous data cannot be corrected.

An object of the present invention is to provide a signal acquisition circuit that can extract a predetermined control signal from the plurality of pieces of data without error.

In the present invention, the control signal is captured only when the vertical synchronization pulse is extracted from the input signal and the control pattern is extracted, and when the vertical synchronization pulse is not extracted, the capture of the control signal is stopped.
In addition, data capture is started, and if a control pattern is extracted at that time, data capture is stopped and data capture is started again from the next data.

The present invention will be described in detail below using specific examples. First, the principle of operation will be explained using the time chart shown in FIG.

FIG. 1 shows a time chart near the vertical synchronization pulse of the video signal. Figure 1a shows an odd number field, and figure 1b shows an even number field.Data 1 is entered sequentially from the horizontal period following the control signal 3, and 245 data 1 are entered in both the odd and even fields in one vertical period. There is.

A time chart near the control signal 3 is shown in FIG. 2, and will be explained below. FIG. 2a shows the video signal, and FIG. 2b shows the correctly extracted vertical synchronization pulse 4. Figures c to f in the figure show vertical synchronization pulses when the timing of the vertical synchronization pulses is incorrect. In this embodiment, the horizontal period following the vertical synchronization pulse 4 is the control signal 3.

For example, if the vertical synchronization pulse is generated at an early timing as shown in Figure 2c, the next horizontal period
It takes in c'' as a control signal and starts the operation. However, since signal c'' is zero, it is treated as an error.
Next, an operation is started to take in the horizontal period of the signal c' as the first data, but it is similarly treated as an error. Next, the horizontal period of the signal c is taken in as the third data, and when a control pattern matching pulse is outputted by the control pattern extraction circuit described later, the recording address counter is reset by the same pulse. No control signal is taken in here. Then data 1 for the next horizontal period
is taken as the first data and the operation begins.
Thereafter, the second and third data are taken in in order. If the timing of the vertical synchronization pulse is output early in this way, the capture of the control signal is stopped. If the control pattern is extracted after that,
Since the recording address counter is reset by this pulse, data is taken in in the correct order. The same operation is performed in the case of FIG. 2d.

Next, in the case of FIG. 2e, data 1 of the next horizontal period is fetched as the first data, and data are fetched in the order of data thereafter. Next, in the case of f,
Data 2 of the next horizontal period is fetched as the first data, and thereafter data are fetched one by one. If the vertical synchronizing pulse is delayed by two horizontal periods or more in this way, data will be taken in with a shift.

Next, the bit structure of data within one horizontal period will be explained in more detail using the time chart of FIG. FIG. 3a shows an example of the bit structure of a data frame, and FIG. 3b shows an example of the bit structure of a control signal frame. First, the data frame consists of a 4-bit cue signal 5, a total of 8 words (6 data words, and 2 correction words) of 14 bits each, and a 16-bit CRCC for a total of 132 bits. Next, the control signal frame includes a 4-bit cue signal 5, a 56-bit control frame extraction pattern Cp, a 56-bit control signal C, and a 16-bit cue signal 5.
It consists of a total of 132 bits of CRCC. Here, the cue signal 5 is provided for data strobe timing adjustment. Furthermore, the control frame extraction pattern Cp is a pattern for distinguishing whether the same frame is a data frame or a control frame.

Here, the control frame extraction pattern Cp is composed of 56 bits, for example, by repeating "1100", but if the same frame pattern alone is used to distinguish between a data frame and a control frame, the pattern Cp in the data frame exists, the data frame data may be mistaken for a control signal, causing malfunction. For example, if the presence or absence of a P or Q correction code, which is one of the control signals, is incorrectly detected, it will become impossible to correct the erroneous data, and if a digital dubbing prohibition code is incorrectly detected, the dubbing function will not work properly. It becomes an obstacle. The present invention, including its protection method, will be explained in detail with reference to the block diagram of an embodiment shown in FIG.

The video signal A is separated into data and a synchronization signal by a data separation circuit 6 and a synchronization separation circuit 19, respectively. First, data is strobed into a data strobe circuit 8 by a strobe pulse 7, and then input into a shift register 12 by a shift pulse 11. The output 14 of the shift register 12 is input to the shift register 16 by a shift pulse 17.
On the other hand, the parallel output 10 of the shift register 12 is input to a matching circuit 13 set in a predetermined pattern. The matching circuit 13 outputs an output 39 at the moment when the preset control pattern and the input 10 match. The match circuit output 39 then sets a flip-flop 38. This flip-flop output 1
8, the shift pulse 17 of the shift register 16
gate. Therefore, when the coincidence circuit output 39 is received, the shift pulse 17 is passed and the input signal 14 is input to the shift register 16. That is, only when a control pattern is extracted, a control signal is extracted to drive a control system (not shown).

Next, from the synchronization signal, the horizontal synchronization signal generation circuit 2
0 and the vertical synchronization signal generation circuit 32 surrounded by broken lines
horizontal synchronization signal 27 and vertical synchronization signal 34
generate. First, this horizontal synchronizing signal 27 is counted by the recording address counter 35. Further, the vertical synchronization signal generation circuit 32 inputs the synchronization signal 40 to the shift register 22 using a predetermined shift clock 20. Inputting the parallel output signals of the shift register 22 to a matching circuit 24 set in a predetermined pattern,
The matching circuit 24 is set to output an output 25 only when the synchronizing signal pattern matches the vertical synchronizing signal pattern. If the matching circuit output 25 is not output within a predetermined time, it is detected by the detection circuit 26, and the pseudo vertical synchronization signal 28 delayed by the shift register 29 is selected by the selection circuit 30 based on the detection output 15. and output as a vertical synchronizing signal 31. Here, the shift register 29 is shifted by a shift pulse 41, and the shift pulse and the number of stages are set so that the delay time is an integral multiple of the vertical synchronization signal period. Then, the recording address counter 35 is cleared by the vertical synchronizing signal 34 via the delay circuit 33. Further, if the vertical synchronization signal pattern 25 is not extracted, the recording address counter 35 is detected by the detection output 15.
, and the shift register 16 starts counting.
The strobe of the control signal at is stopped. Note 4
Reference numeral 1 denotes an audio data capture circuit which sequentially captures the audio data 1 and re-captures the audio data according to the output of the recording address counter 35.

As described above, according to the present invention, only when a vertical synchronizing signal pattern is obtained and a correct control pattern is obtained, the control pattern is extracted and the control signal is latched into the shift register 16. Next, data is sequentially fetched from the next horizontal period of the control signal.
Furthermore, if the vertical synchronization signal pattern is not extracted, the control data capture is stopped and data capture is immediately started. If a control pattern is extracted at this stage, the recording address counter 35 is cleared and the measurement is re-measured from the next horizontal period, and furthermore, the data is re-captured. By doing so, it is possible to reduce errors in control signals and maintain data continuity.

[Brief explanation of the drawing]

Figures 1a and b show time charts of part of the video signal, Figure 2a is an enlarged view of the main part of Figure 1, and Figures b to f are time charts showing five examples of vertical synchronization signal generation. It's a chat. 3a and 3b are two data pattern diagrams, FIG. 4 is a partially enlarged view of the data pattern in FIG. 3, and FIG. 5 is a block diagram of an embodiment of the present invention. 1...Data, 2...Vertical synchronization signal, 3...Control signal, 6...Data separation circuit, 12, 16, 2
2, 29... Shift register, 13, 24... Coincidence circuit, 19... Sync separation circuit, 20... Horizontal synchronization signal generation circuit, 26... Detection circuit, 30... Selection circuit, 35... Recording address counter, 41
...Data acquisition circuit.

Claims (1)

[Claims] 1. In a circuit that takes in each of the above data from a digital signal group including at least a digitized synchronization signal pattern, a control signal pattern and control data, and a plurality of data groups, a circuit for detecting a synchronization signal pattern from the digital signal group. 1
a detection means, a second detection means for detecting a control pattern from the digital signal group, and a control data acquisition means for importing control data only when the detection outputs of the two detection means are obtained in a predetermined relationship. A signal acquisition circuit comprising: