JPS63288319A - Image generating device - Google Patents

Abstract

PURPOSE:To execute the processing at a high speed by executing read-out of an intermediate code from a bucket, and a setting processing to its intermediate code processing part, by a hardware, and increasing a speed of each processing. CONSTITUTION:A first information processing part 320 for dividing a bit map (BM) CPU into two, and executing the processing by a software, and a bucket switch part 330 constituted of a hardware are connected through an internal bus B302 and B303, respectively by a P-ROM 305. The bucket switch part 330 transfers an intermediate code stored in the P-ROM 305 to a font image write part 311 of a BM write part 31, a graphic image write part 316 and a print engine interface 307, through an internal bus B305. The P-ROM 305 uses the FIFO 305 constituted of a hardware, such a processing as a management of a storage address by the CPU is omitted, and the throughput is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image generating device that prints data sent from a data processing device such as a host computer.

"Prior Art" In general, data sent from a host computer to an image generating device includes print data indicating the actual print pattern and control data for controlling the printing method and print engine mode for controlling the six image generating devices ff. The device (hereinafter simply referred to as a controller) processes this data, converts it into a dot image to be actually printed, and supplies it to a print engine that performs printing.

Conventionally, print controllers have used a first-in, first-out (FIFO) buffer for internal data flow in order to synchronize input from a host computer and output processing with a print engine.

The print controller temporarily stores input data in a buffer, then sequentially performs packet processing asynchronously with the data input, and stores the data in a FIFO.

The main processing contents include protocol analysis, temporary editing of print data, conversion of the temporary editing result into a packet (intermediate code) that can be easily drawn in a bitmap memory, and storage of the intermediate code in the memory. Temporary editing of print data refers to determining the print position for each sent print data according to the protocol analysis results. Therefore, the intermediate code representing the print data is the pattern code of the print data, the drawing on the bit map. This includes addresses, etc. When outputting, the intermediate code is converted to a bit image and drawn in bitmap memory.

The processing of writing code to FIFO, reading code from PIFo, and setting code to the drawing section and print engine section are both processed by software by the CPU in the controller to increase data processing efficiency. The applicant filed the application earlier.

"Problems to be Solved" As mentioned above, when FIFO data processing is performed using CPLI software, although the overall data processing efficiency is improved, the processing time is too long. Due to the demand for data processing, it has become necessary to use hardware for high-speed processing.In particular, for the part that reads the packet from the FIFO, it is only necessary to set the middle code in the packet in the middle code processing section. The purpose of this is to ovalize the readout portion using hardware to increase processing speed.

"Means to Solve the Problems" The present invention has been made to solve the above problems, and the specific means thereof include: a storage device that can access data of a predetermined bit length; an input means for writing data, a first counting means for storing a write address updated in synchronization with a data write sequence to the storage device, an output means for reading data from the storage device, and a first counting means synchronized with the read sequence from the storage device. a second counting means for storing a read address that is updated by a second counting means, which is counted in synchronization with a write sequence of a predetermined data length to the storage device, and is subtracted in synchronization with a read sequence of the predetermined data length; A third counting means for counting the number of data in units of a predetermined data length, and a selection for selecting which processing device among the plurality of processing devices the subsequent data is to be transferred based on the data read from the storage device. means, signal generating means for generating a signal for transferring data read from the storage device to a predetermined processing device, fourth counting means for counting in synchronization with the reading sequence from the storage device, and the fourth counting means. and initializing means for initializing the first to fourth counting means.

"Operation" The specific means of the present invention is as described above, and includes a selection means for selecting and transmitting subsequent data among a plurality of processing devices according to data read from a storage device, and a selection means for selecting and transmitting subsequent data among a plurality of processing devices, and The signal generation means that generates the signal for
It is possible to speed up the data processing of reading the intermediate code from O and setting it in the drawing section and the print engine section.

Embodiments Hereinafter, embodiments of the present invention and their effects will be described using an electrophotographic printer as an image generating device with reference to the accompanying drawings.

<Configuration of electrophotographic printer> First, the general structure of the printer and controller will be explained.

FIG. 1 shows the configuration of a processing system using a printer system 1o capable of drawing graphics, which is an embodiment of the present invention.

In order to improve the throughput of the data processing device 1, the data from the general-purpose data processing device 1 is temporarily stored in an external file buffer 2, and then transferred to the printer system 10.
is output to.

The printer system 10 includes a bitmap type data processing module fi (BMU) 3, a print engine 4 using an electrophotographic process and a laser, and an external paper feed unit 5.
It consists of attached devices such as a sorter 6 and a sorter 6.

FIG. 2 shows the external appearance of the printer system 10. The print engine 4 incorporates the bitmap type data processing device 3 described above, and can be connected to an external paper feed unit 5 and a sorter 6 as accessories. Also, on the upper front side of the print engine 4, there is a display panel 4 that displays the system status and has keys arranged for simple operations.
4 is installed.

FIG. 3 shows details of the display panel 44. Here, 901 to 903 are input keys, and 910 to 91
8 is a display element. A key 901 is a PAUSE key for temporarily stopping the printing operation. key 902
is TESll to start TESTPrint.
-, key 903 is a shift key, key 902 is
CANC to interrupt printing by pressing at the same time
It becomes EL-1r-.

FIG. 4 is a schematic block diagram of printer system 10.

The bitmap type data processing device 3 includes a bitmap control section (BMC) 30, a bitmap RAM (BM-RAM) 32 for bitmaps, a bitmap writing section (BMW) 31 for drawing on this BM-RAM 32, and a font section. Consists of 33. Connection with print engine 4 is via bus B for control data (number of sheets, accessory control, etc.)
3 and a bus B4 for image data, the print engine 4 is mainly composed of three controllers.

First, the interface control section (IFC) 40 processes control data from the bitmap control section 30, controls the operation panel, and controls the print engine 4 through the internal bus B5.
Controls the overall timing.

The electrophotographic control section 41 controls the electrophotographic processing section 45 in accordance with data sent from the interface control section 40 through the internal bus B5.

The print head control unit (1) HU) 42 is connected to the internal bus B.
In order to write the image data sent from the bitmap writing section 31 through the internal bus B5, the light emission of the semiconductor laser of the print head section 43 and the rotation of the polygon motor are controlled according to the information sent from the interface control section 40 through the internal bus B5. do.

In addition, the external paper feed unit 5 and the sorter 6 are also connected to the internal bus B5.
It is controlled by the interface control unit 40 through the interface control unit 40.

<Configuration of Conventional Controller> FIG. 5 is a block diagram of a conventional bitmap control section 30. Bitmap system wf430 uses internal bus B50
It consists of several blocks connected by 1. B
The M-CPU 301 is a central control unit of the bitmap data processing device 3, and communicates with the data processing bag M1 through the data processing device interface 308, converts print data, and writes the bitmap writing interface 306. In addition, it controls the bitmap writing section 31 and print engine interface 30.
7 to control the print engine 4. SYS-R
AM302 stores the program of BM-CPul301. SYS-ROM303 is BM-CPU
This is the working storage area 301, and is used to store the stack and basic flags.

The R-buffer 304 is a buffer for communication with the data processing device 1, and its purpose is to desynchronize communication between the processing program of the FIM-CPU 301 and the data processing device 1.

The P-RAM (FIFO) 305 stores data from the data processing device 1 as an intermediate code converted from font attributes for printing.

The print engine interface 307 is an interface with the print engine 4, and provides JOB information such as the number of prints and JOB information such as print commands.
B control commands are exchanged with the print engine 4 interface via bus B3.

FIG. 6 shows a detailed block diagram of the bitmap writing section 31. The functions of the bitmap writing section 31 are roughly divided into BM,
-Drawing function to RAM32 and BM-R when printing
It is divided into a function of outputting AM32 data to the print engine 4.

The function of drawing to the BM-RAM 32 is further divided into two parts: drawing of lines and circles performed by the graphic image writing section 316, and font drawing performed by the font image writing section 311. This is a logic section that operates with intermediate code sent from the bitmap control section 30 through the bitmap control section interface 317, and the graphic image writing section 316
Most of the processing in the font image writing unit 311 involves analyzing the parameters in the intermediate code and drawing them in the BM-RAM 32, whereas most of the processing in the font image writing unit 311 involves writing the font through the font unit interface 314 according to the data in the intermediate code. The font image read from part 33 is BM-
Draw to RAM32.

On the other hand, the function of outputting data during printing is performed by the print head control unit interface 315.

That is, the bitmap control unit 30 and the interface 3
When the print start code sent via the print engine 17 is received, the print head control unit 42 of the print engine 4
According to the synchronization signal sent through bus B4 from
The data in the BM-RAM 32 is transferred to the print head control unit 42.
Output to.

<Configuration of Control Unit of the Present Invention> FIG. 7 shows the configuration of the bitmap control unit 30 of the present invention and its connection with the bitmap writing unit 31.

The configuration of the bitmap control section 30 is different from the configuration of the conventional bitmap control section shown in FIG.
Divide the PU (301 in Figure 5) into two.

A first information processing unit 320 that performs processing using software, and a bucket switch unit 330 that includes hardware.
and are respectively connected to internal bus B50 by P-RAM305.
2 and B503, and the packet switch unit 330 transfers the intermediate code in the P-RAM 305 to the font image writing g3 of the bitmap writing unit 31.
11. Internal bus B for the graphic image writing unit 316 and print engine interface 307
505. In the first information processing unit 320, data from the data processing device interface 308 is temporarily stored in the R-buffer 304 via the internal bus B501, and then sequentially processed.The main processing contents include protocol analysis, There is provisional editing of print data, conversion of the provisional editing result into an intermediate code that can be easily drawn in the BM-RAM 32, and storage of the intermediate code in the P-RAM 305. Temporary editing of print data refers to determining the print position for each print data sent according to the protocol analysis results. Therefore, the intermediate code representing the print data is the pattern code of the print data, the drawing address on the bitmap. etc. are included.

In the conventional method, the P-RAM 305 uses a memory accessed by the CPU, but in this embodiment, the P-RAM 305 uses a hardware configuration FIFO (hereinafter referred to as P-RAM).
(referred to as IFO) 305 is used.

This is to improve throughput by omitting processing such as storage address management by the CPU.

FIG. 8 shows a configuration example of the first information section 320, where 321 is a CPU that performs processing, 322 is a system ROM in which the CPU program is written, and 323 is a system RAM used as a working storage area for the CPU. be. Further, the timer 324 allows the CPU 321 to manage timing.

<Flow of the first information processing section> FIGS. 9 to 13 show the flow of the first information processing section of the bitmap control section 30.
3 is a flowchart showing the processing of the information processing section 320.

In FIG. 9, first, when the power is turned on (step #1, hereinafter steps will be omitted), after internal initialization (#2), the received data from the data processing device 1 is stored. After clearing the R-buffer 304 (#3),
Initialize the control flag (#4>, specifically,
Clears LPWRITE indicating that a temporary image is being edited in the received data processing routine. In addition, FIFO3
05 is cleared by hardware when the power is turned on. Then, in preparation for intermediate code creation, font attributes are read from the font unit 33 in order to determine the font format of print data (#5).

After completing these preparatory operations, enter the main loop (#6 to #8
), the processing in the main loop is to analyze the received data and convert it to intermediate code. The data flow is as follows. First, data from the external data processing equipment is input to the R
- stored in buffer 304; This received data is received when there is space in the intermediate code memory PIFO 305 (#
6: No), when there is data in the R-buffer 304 (
#7), received data processing routine (#8, or 10th
) is converted into an intermediate code and stored in the FIFO 305.

In other words, for the P1-map writing section 31, the PIF
Data processing is transferred in the form of an intermediate code via O305, and this intermediate code is sent to the BM-RAM 32 of a pattern according to the pattern selection and font size to the phono 1.
It contains the calculated value of the drawing address for , and can be said to have been virtually edited. Also, at the time of initialization, the bitmap writing section 31 reads the font attributes.
This is because temporary editing is performed asynchronously with the character drawing in .

<Received data processing> FIG. 10 shows the flow of received data processing (#8).

Received data is classified into the following four types.

◇IFC related codes (print engine related codes) ◇JOB control codes (JOBS 5TART, PAG
E EJECT) ◇ Format control code ◇ Print data (character code, graphic code) First, in the case of print data, (#32.#35゜#37.#3
9. No in #41>, temporary image gA concentration (L
PWRI TE=1) (#43, #44), convert it to the intermediate code of the corresponding format and save it to PIFO3.
Output to 05. In other words, in the case of character code (#4
5) is the same as the format to the font/image writing unit 311, and the font pattern address (#4
7), BM- corresponding to the print position on the image area
In the case of a graphic code consisting of a write address (#48) to RAM32, a write mode (#49),
#53) is output in the same format as the command to the graphic image writing unit 316 (#54)
, At this time, in the case of a character code, update the next character printing position (#52), and for both character data and graphic data, at the beginning of the data, indicate whether the packet is character data or graphic data. #46. #54), intermediate code 4 word output f& A bucket write pulse indicating that writing of 1 packet is completed is output (#51. #56).

The IFC related code (#32) is output to the interface control unit 40, but in order to synchronize with the print data, it is output by the FIFO output routine in Figure 22 as an intermediate code of a function type different from the print data. Output to PIFO305 (#32.#3
3).

J' OBI! l There are two I codes: the PAGE EJBCT code used to separate pages, and the JOB ST/RT code used to separate JOBs (page groups) (#35, #37), and JOB 5TART.
:7-Doha1FcrR] Similarly to the continuous code, PIFO3
The PAGE EJECT code output to 05 (#36) is the PAGE EJECT processing routine (11th
Processing is performed according to the method shown in the figure (#38).

If it is a format control code (YES in #39), the format control code is processed (#40).

<PAGE EJECT Processing and Format Control> FIG. 11 shows the flow of PAGE EJECT processing (#38). The PAGF and EJECT processing are performed by FI
FO305-HIHE This is a virtual process when collecting paper as an intermediate cord, and is different from actually discharging paper. 1) AGE EJECT processing is performed during temporary image editing (#81).
An intermediate code indicating PAGE EJECT is output to 05.

In the case of this intermediate code, output a code (packet ID) indicating that the first word is a print engine command in the first word (#83), and after outputting 4 words of the intermediate code (#84), Outputs a packet write pulse indicating that writing of one packet is completed (#8
5) Here, the actual sheet ejecting operation is performed when the print engine interface 307 receives this intermediate code.

After that, in preparation for the next page of M collection, the next printing position is returned to the beginning (#86), and LPWRITE is set to O (#87). These series of operations are performed by setting the LPWRITE flag indicating a temporary image brain collection. (#81
．． #88), prevent empty page output.

Figure 12 shows the format control code processing sequence (#40
) (see Figure 21).

For a return code (#101), move the next print position to the left end (#102), for a line feed code (#103)
, moves the next print position down one line (#104), and when random is specified (#105), updates the next print position after adding an offset value (#106).

FIG. 22 shows the packet ID of the first information processing unit 320 (#33 in FIG. 10), which outputs the packet ID indicating that it is a command to the print engine in the first word to the FTFO 305, and outputs the intermediate code. After outputting 4 words (for 1 packet) (#182), a bucket write pulse is output to the PI FO 305 (#183).

FIG. 13 shows the flow of accepting value opening. When an interrupt is received from the data processing device 1 (# 21 ), data is read from the data processing device interface 308 (# 122 ), and the data is transferred to the R-buffer 304. Write data (#123).

<F　　　　　　FO＞ FIG. 14 shows an example of the FTPO 305.

The P I FO305 uses RAM mainly around the RAM3051.
, the first information processing unit 320 , and peripheral circuits that control timing with the packet switch unit 330 . PIFO
The data stored in 305 is processed in units called packets, and one packet is composed of 5 words (1 word, 16 bits). RAM3051 has 1
Read/write in word units, 3052 to 3052 in Figure 14
It is controlled by a circuit of 3055. Control in units of packets is performed by circuits 3056 to 3058 in FIG. 14. Packet control is performed using a packet counter (in this example, 1
This is done based on a 4-bit up/down counter) 3056. The bucket counter 3056 indicates that the first information processing unit 320 receives one packet as the signal v! , TeleRA via 3101
M 3051 G:l: After the output goes low, it is incremented by the bucket write pulse via signal [3108.

This counter value is checked by the full check circuit 3057, and when it reaches a predetermined count (13107 packets in this embodiment), the FIFO full signal is sent to the signal line 3110.
is output to the first information processing section 320 via. On the other hand, R
The presence or absence of packets on the AM 3051 is checked by an empty check circuit 3058, and a bucket counter 3056
When is 0, the FIFO empty signal is sent to signal line 311.
1 to the packet switch unit 330. When the packet switch unit 330 detects the presence of a packet based on this signal, the packet is taken out and analyzed by the bucket counter 3056 via the signal 113109.
At this time, a packet read pulse is output. The bucket counter 3056 decrements by this pulse.

In word-based control, the packet count is independently
This is performed using two counters 3054 and 3055. First, the write address counter (16-bit counter in this embodiment) 3054 receives data from the RAM 30 from the first information processing unit 320.
This indicates the word data write address to 51.
Signal after writing word! It is counted by the data write pulse via 13105. Further, the read address counter 3055 is the RA of the packet switch section 330.
This indicates the address for reading word data from M3051. After completing one word reading process, the signal 11310
It is counted by the data read pulse through 6.

The write address counter 3054 and the read address counter 3055 only need to use the same method for both up-counting and down-counting.The memory timing control circuit 3052 uses the data write pulse and the signal! ! ! 3106 and is activated by a data read pulse via address selector 305.
3, or when reading and writing occur simultaneously, the first information processing section 320 and the packet switch section 33
To apply weight to 0, signal lines 3103.3104
Set the timing of the write end and read end via i
Each counter is initialized by resetting it with a signal a3107.

Note that the three counters 3054, 3055, and 3056 are cleared by hardware when the power is turned on, and cleared as FIFO.

The packet switch unit 330 sequentially reads the intermediate code into the PIFO 305, and executes the specified intermediate code processing unit () onto-image write@311 according to the intermediate code.
．． Graphic image damage part 316. Control is performed to write an intermediate code of a predetermined number of words to the print engine interface 307).

<Packet switch section> FIG. 15 shows an example of the packet switch unit 330.

The packet switch section 330 includes a packet ID latch 3301 for instructing which intermediate code processing section should process the packet, and a packet word counter 330 for counting the number of processed words in one packet.
2, a FIFO read timing control 3303 that controls the extraction of one intermediate code from the PIFO 305, and an intermediate code setting timing control 3304 that controls the timing of setting the intermediate code to the intermediate processing section.

The packet switch section 330 is not setting one packet to the intermediate code processing sections 307, 311, and 316 (according to the packet word counter output 3122),
The graphic image writing unit 316 and the font image writing unit 311 are not processing packets (BUSY3).
126), print), engine 4 is not printing (due to engine BUSY3130), and P I
When there is a packet/sheet to be processed in FO305 (F
(IFO empty 3111) operation starts.

The operation of the packet switch section 330 will be described below with reference to the timing charts of FIGS. 15 and 16 and FIG. 17.

(1st word in packet) When the four conditions for starting the operation are satisfied, the FIFO read timing control unit 3303 controls the PIFO 30
Read the first word data from 5, at this time 1
The word number is information for specifying the intermediate code processing section of the font image writing section 3119 that processes the packet, and since this does not need to be set in the intermediate code processing section, it is necessary to set it in the intermediate code processing section. The intermediate code timing control 3304 that generates the timing signal is not operated. This judgment is made by the signal [31
This signal and the data read pulse 3106 set the first word data in the packet ID latch 3301, and the data read pulse 3106 sets the data in the packet word counter 3.
302 is incremented.

Bucket set in packet ID latch 3301!・
The intermediate code processing section is specified by the data of the first word. That is, bit 15 of the first word specifies whether the packet is print data or a print engine command, and bits 71 and 14 specify whether the packet is print data or a print engine command.
1 or the graphic image writing section 316 is specified. This 2-bit data is stored in the packet ID latch 3301, and three select signals (312
0, 3121, 3131> and is output by three intermediate code processing units (font image writing unit 311, graphic image writing unit 31) that process the packet.
6. Specify one of the print engine interfaces 307).

FIG. 17 shows a timing chart of the packet switch section 330, and here shows processing when the graphic image writing section 316 is designated as the intermediate code processing section.

(2nd to 5th words in the packet) Reading and setting of one word of data is performed by two timing control units 3303 and 3304. First, FIFO read timing control 3303
A data read pulse requesting data output to FIFO 305 is outputted from PIFO 305 via signal line 3106, and PIFO 3
A signal is output via signal 113128 to activate the read end 3104 to notify that the data output at 05 has been determined. Upon receiving this signal, the intermediate code setting timing control 3304 outputs a data write pulse to the graphic image writing unit 316, which is the designated intermediate code processing unit, via a signal 13133, requesting the late writing of data. , the write enable signal indicating that the graphic image writing unit 316 is ready to write is the signal! ! 3132, and then stops outputting the data write pulse. At this point, the graphic image writing section 316
Data is written inside. At the same time, the writing section 3]
A signal indicating that the setting to 6 is completed is sent to the signal line 312.
The FIFO read timing control unit 3303 receives this signal 8 and stops outputting the data read pulse via the signal edge 3106. As a result, the read address counter 3 in the FTPO 305
055, the packet word counter 3056 is incremented, and the FIF of 1 word is incremented.
Reading from O305 and setting to graphic image writing unit 316, which is an intermediate code processing unit, are completed.

Thereafter, the data reading and setting are repeated in the same manner, and when the processing of one packet is completed, a packet read pulse indicating that the processing of one packet has been completed is outputted from the packet word counter 3302 via the signal 113109. The packet counter 3056 in the PIFO 305 is decremented.

This signal also clears the packet word counter itself and returns it to the initial state. In addition, in the specified intermediate code processing section, in order to prevent the packet switch section 330 from restarting the operation during processing, when the data of the fifth word is received, it is indicated that the processing is in progress. BUS
A Y signal is outputted via the signal line 3126, and when one packet is processed, the output is stopped and the packet switch unit 330 is allowed to resume operation. Thereafter, the packet switch unit 330 starts operating again if the above four operating conditions are satisfied (see FIG. 17). Note that the packet word counter 3302 is cleared by hardware when the power is turned on. Also, while the signal 3122 is being input, the packet ID latch 3
301 each select signal 3120.3121.3131
are all configured to be "Low".

Graphic Image Writing Unit> FIG. 18 shows a detailed block diagram of the graphic image writing unit 316.

The graphic image writing unit 316 operates by setting the intermediate code stored in the PIFO 305 by the packet switch unit 330, and when the setting of the intermediate code from the packet switch unit 330 is completed, the graphic image writing unit 316 stops the graphic image being drawn. BM-
A graphic image is drawn in the RAM 32. After the drawing is completed, the GBUSY signal is set to "Low" to notify the packet switch unit 330 that the drawing has ended.

Note that the graphic image writing section 316 receives packet data only when the graphic image writing section select signal is "IIi", and the graphic image writing section 316 is cleared by hardware when the power is turned on. Ru.

<Font Image Writing Unit> FIG. 19 shows a detailed block diagram of the font image writing unit 311.

The font image writing section 311 operates according to the data in the intermediate code by setting the intermediate code allocated to the FIFO 305 by the packet switch section 330, and the font image writing section 311 operates according to the data in the intermediate code. - If the start address of writing to RAM 32, writing mode, font width, and font height are set, drawing is automatically performed according to the set values.

The font image writing unit 311 calculates a font address and a write address to the BM-1”tAM 32 for each piece of data, and a drawing control unit 317 for drawing the font data to the BM-RAM 32 and a font pattern size. It consists of two parts: r + number part.

The drawing control unit 317 includes the packet switch unit 33
After setting the font start address, writing setting address to BM-RAM 32, and writing mode by 0, the FBtJSY signal indicating whether drawing is in progress or the end of drawing is sent to signal line 3162.
If it becomes “Hi” via the BM-RA
Starts drawing font data to M32, calculates the font address and write address to BM-RAM32 for drawing the next data every time one data is written, and at the same time signals the clock indicating the end of one data drawing. line 3165
Output via. This drawing operation of the drawing control unit 317 is performed continuously until the FBtJSY signal becomes "LOW".

The part that counts the font pattern size outputs a latch ■ that stores the character width of the font, a counter ■ that counts the character width, a counter ■ that counts the height of the characters, and an FBUSY signal 3162 that indicates when drawing is in progress and when drawing has ended. It is refined from a flip-flop (hereinafter referred to as ff) for

This part is an AND gate output of a signal for setting the font pattern size (word counter 5 indicating that the data is the 5th word of one packet, data write pulse 3133, and font image writing unit select signal 3121). ) via the signal line 3163, the character width is set in the counter ■, the width of the character is set in the counter ■ and the latch ■, and at the same time, the PB with ff■ set is set.
The drawing control unit 31 uses the USY signal as “t(i”)
Start operation 7. At counter ■, 1fal
A clock output from the N control unit 317 for each M image is counted via the signal line 3165. When the count ends), outputs ripple carry 3164 indicating that writing of one line of ont is completed,
The character width setting value set in the latch (■) is reloaded, and this ripple carry 3164 is also output to the drawing control unit 317 and used for calculating the dot map write address. When the counter ■ finishes counting the height of the characters, a ripple carry signal t! indicates that the counting of the pattern size of 1 font has finished. ? , 3166 and resets ff■)・
Then, the FBUSY signal is set to "Low" to notify the packet switch section 330 that drawing of one font has been completed, and the operation of the drawing control section 317 is stopped.

Here, the G BUS 'l' signal via the signal 13161 indicating that the graphic image writing section 316 is in operation and the FBUSY via the signal [3162 indicating that the font image writing section 311 is operating are connected to the OR gate. The packet switch unit 33 is sent via the signal line 3126 as a BUSY signal indicating that the serial bitmap writing unit 31 is in operation.
Sent to 0.

Note that the font image writing section 311 receives and processes data only when the font image writing section select signal is "Hi". Clearing is performed as the input section 311.

<Print Engine Interface> FIG. 20 shows an overview of the print engine interface 307.

5PIF in print engine interface 307
Among the intermediate codes stored in O305, print engine commands (IFC-related codes, JoBltiq@codes (see FIG. 10)) are processed.

This part of the processing is performed by the packet switch section 330.
These are the reception of print engine commands retrieved from the IFO 305 and the transmission of commands to the print engine 4. Here, the pudding) engine command is
When the code is PAGF, F, or JECT, BM-RA is written in the bitmap writing section 31 during printing.
Since it is necessary to interrupt the drawing operation to M32, the engine B LT S Y signal is output through the signal line 3130 while receiving the intermediate code, and the print end signal output from the print engine 4 after printing is completed. The engine BUSY signal continues to be output until the engine BUSY signal is input via the signal line 373. Print engine command is PAGEE
If it is not a JF, CT code, it has nothing to do with the operation in the bitmap writing section, so there is no need to stop the operation in the packet switch section 330 during command processing, and the engine BUSYm is not output.

Note that the print engine interface 307 receives a print engine interface select signal 313.
The print engine interface 307 receives packet data only when 1 is "Hi", and the print engine interface 307 is cleared by hardware when the power is turned on.

<Image area> Next, we will explain the concept of image area.

FIG. 21 shows an example of this.The part indicated by the total area A1 corresponds to the size of the paper,
This corresponds to the area set within M. The margin area A2 is a blank space when printing is actually performed on paper, and the print data is drawn in the remaining image area A3.

Printing starts from the upper left of image area A3,
Characters are printed sequentially according to the printing direction AIO. If a line feed code is input during the process, the next printing position is moved by the line feed width AI2 in the line feed direction All. When the return code is input, the next printing position moves to the return position ηA13 at the left end of the image area.

"Effects" The present invention has the specific means and effects described above, and reads the intermediate code from the packet and sets the intermediate code to the intermediate code processing section using hardware, thereby increasing the processing speed of each of the above processes. Therefore, it is possible to provide an image generation device capable of high-speed processing.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a processing system using the printer system 10, FIG. 2 is a schematic perspective view of the printer system 10, FIG. 3 is a plan view of the display panel 44, and FIG. 4 is a schematic diagram of the printer system IO. , 513th? 1 is a block diagram of a conventional bitmap control section 30, FIG. 6 is a detailed block diagram of a bitmap writing section 31, and FIG. 7 is a configuration of the bitmap control section 30 according to the present invention and its connection with the bitmap writing section 31. Block diagram showing 8th
9 is a block diagram of the first information section 320, FIGS. 9 to 13 are flowcharts showing the processing of the first information section 320, and FIG. 9 is a flowchart of the main routine.
Figure 10 is a flowchart of received data processing, Figure 11 is a flowchart of PAGE EJECT processing,
Figure 2 is a flowchart of format control code processing, Figure 13 is a flowchart of reception interrupt routine, and Figure 14 is P
A circuit diagram of the IFO 305, FIG. 15 is a circuit diagram of the packet switch section 330, FIG. 16 is an explanatory diagram showing the contents of one packet, FIG. 17 is a timing chart of the packet switch section 330, and FIG. 18 is a graphic image writing diagram. Part 3
19 is a detailed block diagram of the font image writing unit 311, FIG. 20 is a schematic diagram of the print engine interface, FIG. 21 is an explanatory diagram showing an example of the image area, and FIG. 22 is a detailed block diagram of the font image writing unit 311. 1 is a flowchart of the output routine of the 1++Y information processing unit 320 to the bucket. 411. Print engine, 30, Bitmap control unit, 31, Bitmap writing unit, 3
2,,,BM-RAM,305. ,,
F I FO, 320, , 1st information processing section, 3
30, Packet switch section, 3051,...
RAM, 3054. . , write address counter, 3055 , , read address counter, 3056 . ,,Bucket counter, 3301,,,Packet ID latch, 3302,
,,Bucket word counter,3303,,,FIFO
Read timing control, 3304. ,,
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Claims (1)

[Claims] a storage device that can access data of a predetermined bit length;
an input means for writing data to the storage device; a first counting means for storing a write address that is updated in synchronization with a data writing sequence to the storage device; an output means for reading data from the storage device; a second counting means for storing a read address that is updated in synchronization with a read sequence; and a second counting means that stores a read address that is updated in synchronization with a read sequence; a third counting means for counting the number of data in units of a predetermined data length; and a third counting means for counting the number of data in units of a predetermined data length; and a third counting means for counting the number of data in units of a predetermined data length; a selection means for selecting, a signal generation means for generating a signal for transferring the data read from the storage device to a predetermined processing device, and a fourth counting means for counting in synchronization with the read sequence from the storage device. and initializing means for initializing the first to fourth counting means.