JPS6328358B2 - - Google Patents
Info
- Publication number
- JPS6328358B2 JPS6328358B2 JP9804580A JP9804580A JPS6328358B2 JP S6328358 B2 JPS6328358 B2 JP S6328358B2 JP 9804580 A JP9804580 A JP 9804580A JP 9804580 A JP9804580 A JP 9804580A JP S6328358 B2 JPS6328358 B2 JP S6328358B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- gan layer
- layer
- shows
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 150000002500 ions Chemical class 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 229910002601 GaN Inorganic materials 0.000 description 16
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 16
- 239000011701 zinc Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/0004—Devices characterised by their operation
- H01L33/0037—Devices characterised by their operation having a MIS barrier layer
Description
【発明の詳細な説明】
本発明はGaN（窒化ガリウム）ダイオードの製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing GaN (gallium nitride) diodes.
青色発光ダイオードとして利用価値のある
GaNダイオードにあつては、GaN結晶自体Ｎ型
のものしか得られないのでMIS（金属−絶縁層−
半導体）型構造となつている。 Valuable as a blue light emitting diode
For GaN diodes, since the GaN crystal itself can only be of N type, MIS (metal-insulating layer-
It has a semiconductor type structure.
本発明は斯るダイオードをプレーナ形態で得ん
とするもので以下本発明実施例をその工程順に説
明する。 The present invention aims to obtain such a diode in a planar form, and embodiments of the present invention will be described below in the order of their steps.
第１図は第１の工程を示し、表面が平坦なサフ
アイヤ基板１が準備される。 FIG. 1 shows the first step, in which a sapphire substrate 1 with a flat surface is prepared.
第２図は第２の工程を示し、基板１上にノンド
ーブのGaN結晶を約15μｍ厚さに気相成長する。
この成長層はキヤリア濃度が1019cm-3程度のN+
型を呈し、以下N+型GaN層２と称す。 FIG. 2 shows the second step, in which a non-doped GaN crystal is grown on the substrate 1 in a vapor phase to a thickness of about 15 μm.
This growth layer has a carrier concentration of about 10 19 cm -3 N +
It exhibits a type of GaN layer 2, and is hereinafter referred to as an N + type GaN layer 2.
第３図は第３の工程を示し、N+型GaN層２上
に、更にZn（亜鉛）をドーブしたＮ型GaN層３を
気相成長する。該層のキヤリア濃度は約1016cm-3
にして、その層厚は約15μｍである。 FIG. 3 shows the third step, in which an N-type GaN layer 3 doped with Zn (zinc) is grown on the N + type GaN layer 2 in a vapor phase. The carrier concentration in this layer is approximately 10 16 cm -3
The layer thickness is approximately 15 μm.
第４図は第４の工程を示し、Ｎ型GaN層３の
一部表面を除いてSi（シリコン）酸化膜４が被着
される。斯る酸化膜の部分的被着はＮ型GaN層
３の全表面にSi酸化膜を被着した後、写真蝕刻法
等で必要部分だけ残すことによりなされる。 FIG. 4 shows the fourth step, in which a Si (silicon) oxide film 4 is deposited on the N-type GaN layer 3 except for a part of the surface. Such partial deposition of an oxide film is achieved by depositing a Si oxide film on the entire surface of the N-type GaN layer 3 and then leaving only the necessary portions by photolithography or the like.
第５図は第５の工程を示し、Ｎ型GaN層３の
一部表面領域５にZnイオンが注入される。Si酸
化膜４は斯る選択注入の際のマスクとして用いら
れる。注入領域５の深さは5000Å程度が好まし
く、このためにはイオン注入時の加速エネルギは
約100KeV、が適当である。又、注入量は十分大
きく1015イオン／cm2程度が必要である。 FIG. 5 shows the fifth step, in which Zn ions are implanted into a partial surface region 5 of the N-type GaN layer 3. The Si oxide film 4 is used as a mask during such selective implantation. The depth of the implanted region 5 is preferably about 5000 Å, and for this purpose, the appropriate acceleration energy during ion implantation is about 100 KeV. Further, the implantation amount needs to be sufficiently large, about 10 15 ions/cm 2 .
第６図は第６の工程を示し、Si酸化膜４を除去
した後、注入領域５上にZnイオン不透過膜６が
被着される。斯る膜はSi酸化膜４の選択被着と同
様にして形成され、その材質としては窒化シリコ
ンが適当である。 FIG. 6 shows the sixth step, in which after removing the Si oxide film 4, a Zn ion impermeable film 6 is deposited on the implanted region 5. Such a film is formed in the same manner as the selective deposition of the Si oxide film 4, and its material is silicon nitride.
第７図は第７の工程を示し、基板１を含む全体
がアンモニア雰囲気中で約1000℃、１時間熱処理
される。斯る熱処理で、Ｎ型GaN層３の膜６で
覆われていない表面からはZnイオンがアウトデ
イフユージヨンによりぬけ出し、従つてキヤリア
濃度にして1018cm-3程度のN+型表面領域７が形
成される。一方、注入領域５内のZnイオンは膜
６のためにぬけ出ることなく、活性化して注入領
域５内のドナーを補償する。このとき、上記第５
の工程でのイオン注入量が十分大きく、従つて上
記補償効果により注入領域５は絶縁領域５ａへと
変質する。 FIG. 7 shows the seventh step, in which the entire structure including the substrate 1 is heat-treated at about 1000° C. for 1 hour in an ammonia atmosphere. Through such heat treatment, Zn ions escape from the surface of the N-type GaN layer 3 that is not covered with the film 6 by out-diffusion, resulting in an N + -type surface with a carrier concentration of about 10 18 cm -3 . Region 7 is formed. On the other hand, the Zn ions in the implanted region 5 do not escape because of the film 6 and are activated to compensate for the donors in the implanted region 5. At this time, the fifth
The amount of ion implantation in the step is sufficiently large, so that the implanted region 5 changes into an insulating region 5a due to the compensation effect described above.
第８図は最終工程を示し、膜６を除去した後、
正電極８及び負電極９が夫々絶縁領域５ａ及び
N+型表面領域７上に被着される。尚、正、負電
極８，９の材質としてはAn（金）及びIn（インジ
ウム）が夫々適当であり、斯る負電極９はN+型
表面領域の存在により該領域との間に良好なオー
ミツク接触を形成する。 FIG. 8 shows the final step, in which after removing the film 6,
The positive electrode 8 and the negative electrode 9 are respectively insulating region 5a and
It is deposited on the N + type surface area 7. Note that An (gold) and In (indium) are suitable materials for the positive and negative electrodes 8 and 9, respectively, and the negative electrode 9 has a good relationship with the N + type surface region due to the presence of the N + type surface region. Forms ohmic contact.
かくして本発明により得られるMIS型ダイオー
ドは、その絶縁層がGaN表面内に埋設形成され
たブレーナ型となり、従つて同一GaN表面内に
複数の絶縁層を形成してモノリシツク型表示装置
等を得ることができ、又ダイオードの正、負電極
を同一面側に設置できるので斯る電極と外部リー
ド線との結合が容易になる。更にこの種ダイオー
ドの特性に重要な影響を及ぼす絶縁層はイオン注
入により形成されるものであるから、その層厚や
濃度を高精度に制御でき、再現性良くダイオード
を製造することができる。 Thus, the MIS type diode obtained according to the present invention is a Brenna type in which the insulating layer is buried within the GaN surface, and therefore a monolithic display device etc. can be obtained by forming a plurality of insulating layers within the same GaN surface. Furthermore, since the positive and negative electrodes of the diode can be placed on the same side, it is easy to connect these electrodes to external lead wires. Furthermore, since the insulating layer, which has an important influence on the characteristics of this type of diode, is formed by ion implantation, the layer thickness and concentration can be controlled with high precision, and the diode can be manufactured with good reproducibility.
第１図乃至第８図は本発明実施例を説明するた
めの工程別断面図である。
３……Ｎ型GaN層、５……注入領域、６……
Znイオン不透過性膜。
FIGS. 1 to 8 are cross-sectional views of each process for explaining an embodiment of the present invention. 3... N-type GaN layer, 5... Injection region, 6...
Zn ion impermeable membrane.
Claims (1)
域にZnのイオン注入を行ない、次いで該領域を
Znイオン不透過性膜で被覆した後熱処理を行な
つて、上記領域内のZnを活性化して該領域を絶
縁性になすと共に、上記領域以外の上記Ｎ型
GaN層表面よりZnのアウトデイフユージヨンを
行なつて斯る表面をN+型に変換することを特徴
とするGaNダイオードの製造方法。1 Zn ions are implanted into a part of the surface region of the Zn-doped N-type GaN layer, and then the region is
After being coated with a Zn ion-impermeable film, a heat treatment is performed to activate the Zn in the above region to make the region insulating, and to
A method for manufacturing a GaN diode, characterized in that Zn is out-diffused from the surface of the GaN layer to convert the surface to N + type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9804580A JPS5723284A (en) | 1980-07-16 | 1980-07-16 | Manufacture of gan diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9804580A JPS5723284A (en) | 1980-07-16 | 1980-07-16 | Manufacture of gan diode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5723284A JPS5723284A (en) | 1982-02-06 |
| JPS6328358B2 true JPS6328358B2 (en) | 1988-06-08 |
Family
ID=14209173
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9804580A Granted JPS5723284A (en) | 1980-07-16 | 1980-07-16 | Manufacture of gan diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5723284A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2540791B2 (en) * | 1991-11-08 | 1996-10-09 | 日亜化学工業株式会社 | A method for manufacturing a p-type gallium nitride-based compound semiconductor. |
-
1980
- 1980-07-16 JP JP9804580A patent/JPS5723284A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5723284A (en) | 1982-02-06 |
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