JPS63267011A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To attain high speed operation by providing the 3rd and 4th field effect transistors whose gates and drains are connected in crossing so as to shift the potential difference of two signals in opposite phase to each other to a required signal level without decreasing the difference. CONSTITUTION:1st and 2nd field effect transistors (TRs) Q11, Q12 whose drains are connected to the 1st constant power supply VDD, the 3rd and 4th field effect TRs Q15, Q16 whose gates and drains are connected in crossing and whose sources are connected to the 2nd constant power supply VSS and the 1st and 2nd diode circuits Q13, Q14 for level shift are provided to the titled circuit. Thus, the amplification factor of source follower circuits IV, V is brought into the unity or over by the operation of the feedback loop where gates and sources of the TRs Q15, Q16 are connected in crossing. Thus, two signals inputted to input terminals I, the inverse of I of negative phase are level-shifted and its potential difference is outputted to an output terminal while being increased more.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit for simultaneously level-shifting two signals having mutually opposite phases.

(Prior Art) A circuit that simultaneously level-shifts two signals having opposite phases to each other is used, for example, when level-shifting an output signal of a sense amplifier of a semiconductor memory device.

Conventional circuits of this type include, for example, the literature (Gallium Arsenide IC Symposium Technical Digest)
GaAs ICSymposium Technica
lOi9est) (1984) P, 119 and Showa 5
There is something disclosed in the 9th Annual National Conference of the Institute of Electronics and Communication Engineers, P, 2-303).

FIG. 3 is a diagram showing a conventional circuit of this type, and the circuit indicated by a symbol ■ in FIG. 3 is the circuit.

This circuit (2) consists of a source follower circuit shown in the figure consisting of normally-on type field effect transistors Q21, Q25 and a Schottky diode Q23, and a normally-on type field effect transistor Q22, Q26 and a Schottky diode Q24. It also includes a source follower circuit indicated by II in the figure.

The internal connection state of each of these two independent source follower circuits I and H is common to both, and this connection state will be explained using the source follower circuit as an example.

The drain of the field effect transistor Q21 is connected to the first constant potential power source vo. The source of Q21 is connected to the anode of Schottky diode Q23. Further, the cathode of this Q23 is connected to the drain of a field effect transistor Q25, the source of this Q25 is connected to the second constant potential power supply vss, and the source and gate of this Q25 are generally short-circuited. Further, the gate of Q21 is connected to the input terminal 2 into which the first signal is input, and the cathode of Q23 is connected to the output terminal Q2 of the second signal.

The connection state between each component in the source follower circuit H is such that the gate of the field effect transistor Q22 is connected before the input terminal to which the second signal is input, and the cathode of the Schottky diode Q24 is connected to the input terminal to which the second signal is input. The source follower circuit I is operated in the same manner as the source follower circuit I except that it is connected to the output terminal Q2 of the source follower circuit I.

According to the circuit (2) described above, when the first signal is input to the input terminal 2 of the source follower circuit I, a voltage almost the same as the voltage of this signal is generated at the point indicated by A2 in FIG. is output. Further, a voltage obtained by shifting the voltage at the point A2 by the clamp voltage of the Schottky diode Q23 is output to the output terminal Q2.

On the other hand, in source follower circuit H, a second signal having an opposite phase to the signal input to input terminal 2 of circuit I is input to its input terminal, and a predetermined value is input to output terminal Q2. A signal that is level-shifted and has a phase opposite to the signal that is output to the output terminal Q2 of the circuit engineer is output.

In this way, this circuit (2) is configured so that the voltages of the signals input to the input terminals 2 and (2) can be level-shifted and output to the corresponding output terminals Q2 and (2), respectively.

(Problems to be Solved by the Invention) However, since the circuitry and circuitry included in the above-mentioned circuit (1) and (2) are originally source follower circuits, their amplification degree is 1 or less. Therefore, there is a problem in that the potential difference between the two signals output to the output terminals Q2 and Q2 is inevitably smaller than the potential difference between the two signals input to the input terminal 2 and the terminal.

Also, since circuit I and circuit II operate independently of each other,
By changing the characteristics of the elements 021 to Q26 that make up the circuit, the potential difference between the two signals of opposite phase input to the input terminals and terminals 2 and the two signals output to the output terminals Q2 and - There is a problem that the potential difference between the two signals may be reversed.

Also, when actually using the circuit (2), a load, especially a capacitive load, is added to the output terminals Q2 and Q2.In such a case, a high level signal is not applied to the output terminals Q2 or Q2. When outputting, since the circuit and the circuit (2) are source 2 lower circuits, the capacitive load is charged at high speed.

On the other hand, in order to output a low-level signal to the output terminal Q2 or Q2 at a fast response speed, it is necessary to discharge the charges stored in these capacitive loads at a high speed. However, this discharge rate is limited by the current flowing through the elements shown by Q25 and 026, so in order to operate the circuit m shown in FIG. 3 at high speed, the current flowing through the elements shown by Q25 and Q26 must be increased. There is a need.

However, if the current flowing through the elements shown by Q25 and Q26 is increased, the amplification degree of the source follower circuits I and H will be lowered. There is a problem in that this results in a result that is contradictory to not reducing the signal potential difference.

An object of the present invention is to solve the above-mentioned problems, to shift the level of two signals having opposite phases to a required signal level without reducing the potential difference, and to achieve high speed and characteristic of the elements constituting the circuit. A semiconductor integrated circuit 1Fr1 that can operate with sufficient margin against changes! It is about providing.

(Means for Solving the Problems) In order to achieve this object, according to the present invention, for example, as shown in FIG. 1, two signals of opposite phases are simultaneously level-shifted using field effect transistors. Configure a semiconductor integrated circuit ■.

In this circuit ■, each drain is connected to the first constant potential power source V
o. first and second field effect transistors Q connected to
N and Ql2, and third and fourth field effect transistors QI5 and Ql6 whose gates and drains are cross-coupled to each other and whose respective sources are connected to the second constant potential power supply Vll, and according to a desired shift amount. first and second diode circuits Q13 and Ql for level shifting, which can be configured with a number of level shifting diodes;
4, and first and second impedance elements QI7 and Ql
8, the gate of the first field effect transistor Q11 is connected to the first input terminal I+ to which the first input signal is input, and the gate of the second field effect transistor Q12 is connected to the second input terminal I+ to which the second input signal is input. Connected to the input terminal port, the source of the first field effect transistor Qll is connected to the third field effect transistor QI5 via the first diode circuit Ql3.
is connected to the drain of the second field effect transistor Q12.
The source of the transistor is connected to the drain of the fourth field effect transistor Q16 via the second diode circuit Q14, the drain of the third field effect transistor GH5 is connected to the second constant potential power supply VSS via the first impedance element QI7, The drain of the four field effect transistor Q16 is connected to the second impedance element 018! The drain of the third field effect transistor Q15 is connected to the second constant potential power supply vss through the transistor, the drain of the third field effect transistor Q15 is the first output terminal Q, and the drain of the fourth field effect transistor QI6 is the second output terminal Ql. .

Further, in carrying out the present invention, it is preferable to use the first and second impedance elements Q17 and 018M as described above, a resistor, or a normally-on type field effect transistor in which the gate and source are short-circuited.

(Function) In such a circuit ■, the first and second input terminal ports,
When a high level signal is applied to and, for example, a high level signal is applied to , and a low level signal is applied to . A circuit consisting of three field effect transistors Q15 and a second field effect transistor QI2
, the second diode circuit QI4 and the fourth field effect transistor QI6 are originally source follower circuits, so the anode of the diode QI3 (
1) and the anode of diode QI4 (point B in Figure 1) output voltages at levels close to the level of the signals input to the input terminals, respectively. An attempt is made to output a voltage whose level is shifted by the clamp voltage of the first diode circuit Ql3 from the voltage at point A to the second output terminal Q1, and a voltage whose level is shifted by the clamp voltage of the first diode circuit Ql3 from the voltage at point A to the second output terminal Ql. Two diode circuit Q
An attempt is made to output a voltage level-shifted by 14 clamp voltages. In this circuit (2), the desired level shift can be achieved by changing the number of level shift diodes constituting the diode circuits Q13 and Ql4. It is possible to output a signal of

By the way, the output terminal Q is the fourth field effect transistor Q.
Since the output terminal Q+ is connected to the gate of the third field effect transistor Q15, a low level signal is supplied to the gate of the element Q15 in response to the above-mentioned input signal, and the output terminal Q+ is connected to the gate of the element QI6. will be supplied with a high level signal. Therefore, element Q1
5 has a high impedance and element Q+6 has a low impedance. Element QI5 with high impedance
tries to make the voltage at the output terminal Q1 a higher voltage, and the element Q16, which has become low impedance, tries to make the voltage at the output terminal Q a lower voltage. The operation of such a feedback loop in which the gates and sources of Ql5 and Ql6 are cross-coupled results in two source follower circuits 1 and 2
Since the amplification degree of is 1 or more, the first and second input terminals I
, and I, respectively, are level-shifted and are output to the first and second output terminals with a larger potential difference.

However, since the amplification degree of the feedback loop described above is large, if left as is, Ql5 and Ql6 will become completely conductive or non-conductive. has the function of maintaining a non-conducting state, so even if the voltage state of the first and second input signals input to the input terminal and terminal respectively changes, the output does not change accordingly. Therefore, if the input signal is a high speed signal, the circuit portion of this feedback loop will not be able to follow this signal. However, in the circuit (2) of the present invention, the impedance element QI7! is connected between the drain of Q15 and the second constant potential power supply v2. , Ql6
An impedance element Q 18178 is provided between the drain of the transistor and the second constant potential power supply Vss.

If an impedance element is provided in this way, for example, when Ql is at a high level and Ql is at a low level,
Due to the presence of Ql7, the level of Ql is lower than the high level in the absence of Ql7, and therefore the impedance of Ql6 in the conducting state is higher than in the case without Ql7.

Therefore, the level of ``is higher than when Ql7 is not present, so Ql5, to which this level is input, will not be completely non-conductive.Also, when Ql is low level and Q is high level, In this case, the impedance element 0
18 functions similarly to Ql7. Therefore, if the resistance values of these impedance elements Q17 and Ql8 are set to appropriate values, the voltages at the output terminals Q and Ql can be changed without making Ql5 and Ql6 completely conductive or completely non-conductive. High level or low level a@ of the subsequent circuit
This makes it possible to create an appropriate voltage that exceeds the voltage.

Next, consider the case where capacitive loads are added to the output terminals Q and Q. First, when outputting high-level signals to terminals QI and ζ, element Ql5 or Ql6 becomes high impedance and no current flows, so that element QI+!
In other words, the current flowing 012M can be utilized more effectively for charging the capacitive load than in the conventional circuit (2). Also, when outputting a low level signal to terminal Ql or Q, element Ql
5 or Ql6 has a low impedance, so discharging occurs smoothly, and even if the current flowing at this time is considerably large, the current decreases when charging the capacitive load, so there is no fear that the amplification will decrease. In other words, circuit operation can be made faster without worrying about the degree of amplification.

In addition, the element Q
Since the feedback loop composed of I5 and Ql8 has a large amplification degree, it can be said that the input potential difference is difficult to reverse.

(Embodiments) Hereinafter, embodiments of the semiconductor integrated circuit of the present invention will be described with reference to the drawings.

The circuit of the embodiment shown in FIG. 1 was used to perform computer simulations to confirm the effects of the present invention, and the transistor model was a Ga transistor with a gate length of 1 um.
A model and parameters adapted to the actual measurement results of AsMESFε■ were used. The program used for this simulation was a circuit analysis program called ASTAP.

In the calculated circuit (2) of the present invention, the field effect transistors indicated by Ql+ and Ql2 are normally-on type FETs with a gate width of 60 um, and the level shift diodes indicated by Ql3 and Ql4 are used as the sources of the normally-on type FETs with a gate width of 60 um. and a Schottky diode with the drain short-circuited, the field effect transistors indicated by Ql5 and Ql6 are normally-off type FETs with a gate width of 120 um, and the impedance elements indicated by Ql7 and Ql8 are normally-on type FETs with a gate width of 30 um. The gate and source of the circuit were short-circuited.

Therefore, in this circuit (2), the second input terminal 11 is connected to the gate of the normally-on field effect transistor Ql+,
A second input terminal I is connected to the gate of the normally-on field effect transistor QI2.

Roughly speaking, the drains of the pixel elements Qll and Ql2 are connected to a first constant potential power source Voolc:, the source of the element Ql+ is connected to the drain of the normally-off field effect transistor Q15 via the Schottky diode QI3, and the source of the element QI2 is connected to the Schottky voltage source. It is connected to the drain of a normally-off field effect transistor QI6 via a diode QI4M. The drain of element Q15 is connected to the gate of element 016 and the first output terminal Ql, and the drain of element QI6 is connected to the gate of element QI5 and the second output terminal Ql. Roughly speaking, the sources of elements Q15 and Ql6 are connected to the second constant potential power supply V.
Connect to SS. In general, the drain of element QI5 is serious.
Second constant potential power supply VS via impedance element QI7
S, and the drain of element Q16 is connected to second constant potential power supply VBB via second impedance element Ql8.

In this case, Vo. is 2V, vss is OV, the first input signal of a sine wave with a center voltage of 1V, an amplitude of 0.2V, and a frequency of 2GHz is input to input terminal 1; This was done by inputting a second input signal having an opposite phase to the signal input to , and examining the first and second output signals output to the output terminals Q and Q, respectively.

FIG. 2 is a diagram showing a first input signal, a second input signal, a second output signal, and a second output signal, with time on the horizontal axis and voltage on the vertical axis. In FIG. 2, i represents the first input signal, q represents the first output signal, i represents the second input signal, and red represents the second output signal.

As is clear from Figure 2, for an input signal with a frequency of 2 GHz and an amplitude of 0.2 V, the output signal is shifted to a predetermined level, but the amplitude is 0.22 V. It can be said that this circuit (2) can shift to a required signal level without reducing the potential difference between two signals having opposite phases, and can operate at high speed.

Note that this invention is not limited only to the above-described embodiments.

In the embodiment described above, impedance element QI7
Although the explanation is given using an example in which Ql8 is a normally-on field effect transistor whose gate and source are short-circuited, the same effect as in the example can be obtained even if this impedance element is configured with a resistor. I can do it.

Further, in the above embodiment, as a preferred embodiment of the present invention, the first and second field effect transistors have the same characteristics, the first and second diode circuits have the same characteristics, and the third field effect transistor has the same characteristics. An example is described in which the fourth field effect transistor and the fourth field effect transistor have the same characteristics, and the first and second impedance elements have the same characteristics. However, within the scope of the purpose of the present invention, the circuit of the present invention can also be used by changing the characteristics of each element depending on the state of input/output signals.

Using specific examples, the following can be considered.

For example, two input signals having different amplitudes and opposite phases are outputted as two signals having the same amplitude and opposite phases, or signal processing is performed in the opposite manner to the above example.

(Effects of the Invention) As is clear from the above description, the semiconductor integrated circuit of the present invention can shift the level of two signals having opposite phases to a required signal level without reducing the potential difference between them, and can also achieve high-speed processing. It also has the advantage of operating with sufficient margin against changes in the characteristics of the elements constituting the circuit, that is, operating resistant to changes in the characteristics of the elements.

Therefore, the circuit of the present invention can be used for level shifting the sense amplifier output of a memory circuit. Also,
Since the degree of amplification is 1 or more, it can also be used as a sense amplifier itself.

Further, the present invention is suitable for application to other circuits as long as they are circuits that simultaneously level shift two signals having mutually opposite phases.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the semiconductor integrated circuit of the present invention, FIG. 2 is a diagram showing computer simulation results of the semiconductor integrated circuit of the present invention, and FIG. 3 is a circuit diagram showing a conventional circuit. be. I+""First input terminal, I, -...Second input terminal Q
+ ”'First output terminal, Ql...Second output terminal Q
I +-...First field effect transistor QI2-...Second field effect transistor QI3-...First diode circuit Ql4-...Second diode circuit Ql5...Third field effect transistor QI6-...Fourth Field effect transistor Q17...First impedance element Ql8...Second impedance element v0°...First constant potential power supply, Vss"'Second constant potential power supply ■...Semiconductor integrated circuit ■, V-・・Source follower circuit. Patent applicant Oki Electric Industry Co., Ltd. I+...First input terminal I+''-Second input terminal Ql--First output terminal Ql...Second output terminal Ql
+-...First field effect transistor QI2-...Second field effect transistor QI3-...First diode circuit Ql4-/Second diode circuit Ql5-/Third field effect transistor QI6-...Fourth field effect transistor Ql? ---First impedance element QI8...Second impedance element v0°--First constant potential power source Vss''-Second constant potential power source FIG. 1 is a diagram showing a circuit of an English embodiment of this invention. 5 7
Time (nsec) Diagram 2 showing the simulation results of the circuit of the British example I2 VDD I2 Diagram 3 showing the conventional circuit

Claims (3)

[Claims] (1) In a semiconductor integrated circuit that simultaneously level-shifts two signals of opposite phases using field-effect transistors, first and second field-effect transistors each having a drain connected to a first constant potential power supply, a gate and a third and fourth field effect transistors whose drains are cross-coupled to each other and whose respective sources are connected to a second constant potential power supply; first and second diode circuits for level shifting; an impedance element, the gate of the first field effect transistor is connected to a first input terminal to which a first input signal is input, and the gate of the first field effect transistor is connected to a second input terminal to which a second input signal is input. an input terminal, a source of the first field effect transistor is connected to the drain of the third field effect transistor through the first diode circuit, and a source of the second field effect transistor is connected to the drain of the third field effect transistor through the second diode circuit. the drain of the fourth field effect transistor is connected to the drain of the fourth field effect transistor, the drain of the third field effect transistor is connected to the second constant potential power source via the first impedance element, and the drain of the fourth field effect transistor is connected to the drain of the fourth field effect transistor connected to the second constant potential power source via a two-impedance element, the drain of the third field effect transistor serving as a first output terminal, and the drain of the fourth field effect transistor serving as a second output terminal. semiconductor integrated circuits. (2) The semiconductor integrated circuit according to claim 1, wherein the first and second impedance elements are resistors. (3) The semiconductor integrated circuit according to claim 1, wherein the first and second impedance elements are normally-on field effect transistors whose gates and sources are short-circuited.