JPS63261869A - Manufacture of diode chip - Google Patents
Manufacture of diode chipInfo
- Publication number
- JPS63261869A JPS63261869A JP9667587A JP9667587A JPS63261869A JP S63261869 A JPS63261869 A JP S63261869A JP 9667587 A JP9667587 A JP 9667587A JP 9667587 A JP9667587 A JP 9667587A JP S63261869 A JPS63261869 A JP S63261869A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- chips
- support plate
- lamination
- retaining plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 235000012431 wafers Nutrition 0.000 claims description 67
- 239000004065 semiconductor Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 7
- 238000010030 laminating Methods 0.000 claims description 2
- 230000002950 deficient Effects 0.000 abstract description 13
- 230000002093 peripheral effect Effects 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 4
- 238000003475 lamination Methods 0.000 abstract 10
- 230000013011 mating Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ダイオードチップの製造方法に関し、半導体
ウェハー、例えばシリコンウェハーまたはシリコンウェ
ハーを複数枚積層したウェハー積層円柱体を所定の寸法
形状のチップに切断後の、良品チップとウェハーの外周
縁部に生じる不良チップとの選別を容易にする方法に関
する。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a method for manufacturing a diode chip, and relates to a method for manufacturing a diode chip, in which a semiconductor wafer, such as a silicon wafer or a wafer stacked cylindrical body formed by stacking a plurality of silicon wafers, is used as a chip of a predetermined size and shape. The present invention relates to a method for easily sorting between good chips and defective chips occurring at the outer peripheral edge of a wafer after cutting.
ダイオードチップは、通常、半導体ウェハー。 Diode chips are usually semiconductor wafers.
例えばシリコンウェハーの表面に所要の不純物を付着さ
せ、ウェハー中に熱拡散させてＰＮ接合を形成させ、第
４図に示すように前記のＰＮ接合を形成させたウェハー
１を９例えばセラミックの支持板２にワックスで接着し
、所定の寸法形状１例えばさいの目状に切断してつくら
れる。高圧ダイオードの場合には、第６図に示すように
、ＰＮ接合を形成されたウェハーを所要枚数積層接着し
て積層円柱体−３とし、その底面を支持板２に接着して
軸方向に所定の寸法形状に切断して積層チップとする。For example, a required impurity is attached to the surface of a silicon wafer and thermally diffused into the wafer to form a PN junction, and as shown in FIG. 2 with wax and cut into a predetermined size and shape, for example, into dice. In the case of a high-voltage diode, as shown in Fig. 6, the required number of wafers on which PN junctions have been formed are laminated and bonded to form a laminated cylindrical body 3, and the bottom surface of the wafer is bonded to the support plate 2 to form a cylindrical body in a predetermined direction in the axial direction. Cut it into a size and shape to make a laminated chip.
このようにウェハーを切断してチップとするとき、第５
図（ａ）に示すような所望の形状良好なチップと同時に
、第５図（ｂ）、（Ｃ）に示すような形状不良のチップ
がウェハーの外周縁部より発生する。ウェハーの積層円
柱体を切断する場合にも、同様に第７図（ａ）に示す良
好な形状の積層チップと、積層円柱体の外周縁部より発
生する第７図（ｂ）、（Ｃ）に示すような形状不良の積
層チップとができる。また、前述のウェハーに不純物を
熱拡散するとき、ウェハーの外周縁部では熱拡散が均一
にすすまず乱れが生じやすい。そのため、ウェハーの外
周縁より０．５〜２ｍｍ程度内側までは電気的特性の不
良箇所が発生しやすく、切断後の形状良好なチップまた
は積層チップでも、外周縁部に位置していたものには電
気特性が不良なものがある。これら形状不良あるいは特
性不良のチップまたは積層チップは選別除去する必要が
あるが、このような選別は、切断終了後支持板を加熱し
てワックスを溶かし、切断されたチップまたは積層チッ
プを支持板からはずした後に、−個ごとにチェックする
ことになるため、多大な選別時間を要するという欠点が
あった。When cutting a wafer into chips in this way, the fifth
At the same time as chips with desired shapes as shown in FIG. 5(a), chips with defective shapes as shown in FIGS. 5(b) and 5(C) are generated from the outer peripheral edge of the wafer. Similarly, when cutting a laminated cylinder of a wafer, a laminated chip with a good shape as shown in FIG. This results in a laminated chip with a defective shape as shown in the figure. Furthermore, when impurities are thermally diffused into the wafer, the thermal diffusion does not proceed uniformly at the outer peripheral edge of the wafer and tends to be disturbed. Therefore, defects in electrical characteristics are likely to occur within about 0.5 to 2 mm from the outer edge of the wafer, and even if the chips or laminated chips are in good shape after cutting, those located at the outer edge may Some have poor electrical characteristics. These chips or laminated chips with defective shapes or characteristics must be sorted out, but such sorting can be done by heating the support plate after cutting to melt the wax and removing the cut chips or laminated chips from the support plate. After removing them, they must be checked one by one, which has the drawback of requiring a lot of time for sorting.
本発明は、上述の欠点を除去して、ウェハーまたはウェ
ハー積層円柱体を切断してダイオードチップとする際に
生ずる不良チップを容易に選別できるようなダイオード
チップまたは積層チップの製造方法を提供することを目
的とする。An object of the present invention is to provide a method for manufacturing a diode chip or a laminated chip, which eliminates the above-mentioned drawbacks and allows easy selection of defective chips that occur when cutting a wafer or a wafer laminated cylindrical body into diode chips. With the goal.
上記の目的を達成するために、本発明においては、半導
体ウェハーまたは複数枚の半導体ウェハーを積層接着し
たウェハー積層円柱体の一主面を支持板の一面に接着し
、前記半導体ウェハーまたはウェハー積層円柱体を所定
の寸法形状に切断してチップとするダイオードチップの
製造方法において、一面に半導体ウェハーの外径より所
定量だけ小径でかつその幅がダイオードチップの外接円
の直径より一若干広いリング状の溝を有する支持板を用
い、該支持板の他面に半導体ウェハーまたはウェハー積
層円柱体の一面を前記リング状の溝と同心に接着し、該
半導体ウェハーまたはウェハー積層円柱体を所定の寸法
形状に切断するとき前記支持板のウェハー接着面にまで
切り込み、その切り込み深さは少なくとも前記支持板の
ウェハー接着面の反対面に設けられた前記リング状の溝
の底にまで達するようにする。In order to achieve the above object, in the present invention, one main surface of a semiconductor wafer or a wafer-stacked cylinder formed by laminating and bonding a plurality of semiconductor wafers is adhered to one surface of a support plate, and the semiconductor wafer or wafer-stacked cylinder is In a method of manufacturing a diode chip, in which a diode chip is produced by cutting a body into a predetermined size and shape, a ring-shaped semiconductor wafer is formed on one side, which has a diameter smaller than the outer diameter of the semiconductor wafer by a predetermined amount, and whose width is slightly wider than the diameter of the circumscribed circle of the diode chip. Using a support plate having a groove, one side of the semiconductor wafer or wafer-stacked cylinder is adhered to the other surface of the support plate concentrically with the ring-shaped groove, and the semiconductor wafer or wafer-stacked cylinder is shaped into a predetermined size. When cutting, the cut is made to reach the wafer bonding surface of the support plate, and the depth of the cut is such that it reaches at least the bottom of the ring-shaped groove provided on the opposite surface of the support plate from the wafer bonding surface.
このように半導体ウェハーまたはウェハー積層円柱体の
切断と同時に支持板が切り込まれることにより、溝の底
の部分でつながっていた支持板は溝の内側の円板状の部
分と外側の部分とに分離されることになる。また、溝の
幅はチップの外接円の直径より広くしであるので切断さ
れた一個のチップまたは積層チップが支持板の内側部と
外側部とにまたがって同時に接着していること゛はあり
えず、どちらか一方の側にだけ接着していることになる
ので、切断後のチップまたは積層チップも支持板に接着
した状態で二群に分離される。支持板の外側部にはウェ
ハーの外周縁部のチップまたは積層チップが接着してい
るので、この支持板の外側部を取り除くことによりウェ
ハーの外周ｍｌに位置する形状不良あるいは特性不良の
チップまたは積層チップをまとめて簡単に除去すること
ができることになる。In this way, by cutting the support plate at the same time as cutting the semiconductor wafer or wafer stack cylinder, the support plate, which was connected at the bottom of the groove, is now separated into the inner disc-shaped part and the outer part of the groove. They will be separated. Also, since the width of the groove is wider than the diameter of the circumscribed circle of the chip, it is impossible for a single cut chip or a stack of chips to be glued simultaneously across the inner and outer parts of the support plate. Since the chips are bonded to only one side, the cut chips or stacked chips are also separated into two groups while being bonded to the support plate. Chips or stacked chips on the outer periphery of the wafer are adhered to the outer side of the support plate, so by removing the outer side of the support plate, chips or stacked chips with defective shapes or characteristics located on the outer circumference of the wafer can be removed. This means that the chips can be easily removed all at once.
以下、本発明の実施例を図面を参照しながら説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例に用いる支持板を示すもので
第１図（ａ）は上面図、第１図（５）は側面図である。FIG. 1 shows a support plate used in one embodiment of the present invention, with FIG. 1(a) being a top view and FIG. 1(5) being a side view.
支持板２はセラミック、ガラスなどからなり、下面にシ
リコンウェハーの外径より所定量だけ小さな径のリング
状の溝４が切られている。溝４の幅Ｗは作製するダイオ
ードチップの外接円の直径より僅か大きくしである。The support plate 2 is made of ceramic, glass, etc., and has a ring-shaped groove 4 cut in its lower surface with a diameter smaller than the outer diameter of the silicon wafer by a predetermined amount. The width W of the groove 4 is slightly larger than the diameter of the circumscribed circle of the diode chip to be manufactured.
この支持板２の上面に、第２図に示すように、シリコン
ウェハーを複数枚積層接着したウェハー積層円柱体３の
底面をリング状の溝４と同心にワックスで接−着する。As shown in FIG. 2, on the upper surface of this support plate 2, the bottom surface of a wafer laminated columnar body 3, in which a plurality of silicon wafers are laminated and bonded, is bonded with wax concentrically with the ring-shaped groove 4.
その後、ウェハー積層円柱体３を軸方向に所定の寸法１
例えば２ｍｍ角のさいの目状に切断する。このとき、切
断は支持板２がそのウェハー積層円柱体３の接着面側か
ら支持板３の下面に設けられたリング状の溝の底に達す
る深さまで切り込まれるように行われる。このような切
断により、第３図に示すように、ウェハー積層円柱体が
積層チップに切断されると同時に、支持板２がリング状
溝の内側部分２ａと外側部分２ｂとに切断分離される。Thereafter, the wafer-stacked cylindrical body 3 is moved to a predetermined dimension 1 in the axial direction.
For example, cut into 2 mm square dice. At this time, the cutting is performed so that the support plate 2 is cut from the adhesive surface side of the wafer stacked cylinder 3 to a depth that reaches the bottom of the ring-shaped groove provided on the lower surface of the support plate 3. By such cutting, as shown in FIG. 3, the wafer stacked columnar body is cut into stacked chips, and at the same time, the support plate 2 is cut and separated into the inner portion 2a and the outer portion 2b of the ring-shaped groove.
支持板の内側部分２ａにはウェハー積層円柱体の内部の
積層チップ３ａが接着しており、外側部分２ｂにはウェ
ハー積層円柱体の外周縁部の積層チップ３ｂが接着して
いる。A laminated chip 3a inside the wafer laminated cylinder is adhered to the inner part 2a of the support plate, and a laminated chip 3b at the outer peripheral edge of the wafer laminated cylinder is adhered to the outer part 2b.
リング状溝の幅が積層チップの外接円の直径より広くな
っているので、支持板の外側部分２ｂと内側部分２ａと
にまたがって同時に接着している積層チップはありえな
いので、積層チップ３ａの接着している支持板内側部分
２ａと積層チップ３ｂの接着している支持板外側部分２
ｂとは完全に分離、することができる。かくして、ウェ
ハー積層円柱体の外周縁部に位置していた積層チップ３
ｂの接着している支持板の外側部分２ｂを取り除くこと
により、形状不良、特性不良の積層チップをまとめて簡
単に除去できる。その後、支持板の内側部分２ａを加熱
してワックスを溶かし、ウェハー積層円柱体の外周縁部
に位置していた不良積層チップを含まない積層チップを
得ることができ、あらためて選別する必要はなくなる。Since the width of the ring-shaped groove is wider than the diameter of the circumscribed circle of the laminated chip, it is impossible for the laminated chip to span the outer part 2b and the inner part 2a of the support plate and be bonded at the same time. The inner part 2a of the support plate is attached to the outer part 2 of the support plate, and the outer part 2 of the support plate is bonded to the laminated chip 3b.
It can be completely separated from b. In this way, the stacked chips 3 located at the outer peripheral edge of the wafer stacked cylinder body
By removing the outer portion 2b of the support plate to which b is adhered, laminated chips with defective shapes and poor characteristics can be easily removed all at once. Thereafter, the inner part 2a of the support plate is heated to melt the wax, and laminated chips that do not include defective laminated chips located at the outer peripheral edge of the wafer laminated columnar body can be obtained, and there is no need to sort them again.
本実施例はウェハー積層円柱体の積層チップ化の場合で
あるが、半導体ウェハー単体のチップ化の場合にも本実
施例の方法が有効であることはいうまでもない。Although this embodiment deals with the case of converting a stacked cylinder of wafers into a stacked chip, it goes without saying that the method of this embodiment is also effective when converting a single semiconductor wafer into a chip.
本発明によれば、半導体ウェハーまたはウェハー積層円
柱体を支持板に接着し、所定の寸法形状に切断してダイ
オードチップまたは積層チップとする際に、支持板を、
ウェハーの接着された面と反対の面に設けたリング状の
溝を利用して、ウェハーの内部に位置するチップの接着
している内側部分と外周縁部に位置するチップの接着し
ている外側部分と−に切断する。According to the present invention, when a semiconductor wafer or a wafer stacked cylindrical body is bonded to a support plate and cut into a predetermined size and shape to form a diode chip or a stacked chip, the support plate is
Using a ring-shaped groove provided on the opposite side of the wafer to the bonded surface, the inner part of the wafer where the chips are bonded is located inside the wafer, and the outside part where the chips are bonded to the outer edge of the wafer is separated. Cut into parts and -.
このようにウェハーまたはウェハー積層円柱体の切断と
同時に支持板を切断し、支持板の外側部分を取り除くと
、ウェハーの外周縁部に発生する形状不良、特性不良の
チップまたは積層チップも一体としてまとめて簡単に除
去できることになる。By cutting the support plate at the same time as cutting the wafer or wafer stacked cylinder and removing the outer part of the support plate, chips with defective shapes, poor characteristics, or stacked chips that occur at the outer edge of the wafer can also be integrated. This means that it can be easily removed.
その後、支持板の内側部分より分離して得られるチップ
または積層チップには、ウェハーの外周縁部より発生す
る不良品は混入していないのであらためて選別を行う必
要はなく、従来に比べて不良のチップまたは積層チップ
の選別時間を極めて少なくすることができる。Thereafter, the chips or laminated chips obtained by separating from the inner part of the support plate do not contain any defective products generated from the outer edge of the wafer, so there is no need to perform further sorting, and there are fewer defects than in the past. The time for sorting chips or stacked chips can be extremely reduced.
第１図は本発明の一実施例の支持板で第１図（ａ）はそ
の上面図、第１図（ｂ）は側面図である。第２図は支持
体にウェハー積層円柱体を接着した一実施例の側面図で
ある。第３図はウェハー積層円柱体を積層チップに切断
し、同時に支持板を内、外側部分に切断分離した一実施
例の状態を示す側面図である。第４図は支持板に半導体
ウェハーを接着しチップに切断する切り込みがいれられ
た状態を示す従来例の斜視図であり、第５図は従来例の
チップの斜視図で、第５図（ａ）は形状良品、第５図（
ｂ）。
（Ｃ）はそれぞれ形状不良品の一例を示す。第６図は支
持板にウェハー積層円柱体を支持板に接着し積層チップ
に切断する切り込みがいれられた状態を示す従来例の斜
視図であり、第７図は従来例の積層チップの斜視図で、
第７図（ａ）は形状良品、第７図（ｂ）、（Ｃ）はそれ
ぞれ形状不良品の一例を示す。
１ 半導体ウェハー、２ 支持板、３ ウェハ第２図
第３凹
第４図
第 ６ 図
（Ｑ） （ｂ） ＣＣ）第７図FIG. 1 shows a support plate according to an embodiment of the present invention, and FIG. 1(a) is a top view thereof, and FIG. 1(b) is a side view thereof. FIG. 2 is a side view of an embodiment in which a wafer-stacked cylindrical body is adhered to a support. FIG. 3 is a side view showing an embodiment in which the wafer stacked columnar body is cut into stacked chips and the support plate is cut and separated into inner and outer parts at the same time. FIG. 4 is a perspective view of a conventional example showing a state in which a semiconductor wafer is bonded to a support plate and cuts for cutting into chips are made, and FIG. 5 is a perspective view of a conventional example of a chip. ) is a good shape product, Fig. 5 (
b). (C) each shows an example of a defective product. FIG. 6 is a perspective view of a conventional example showing a support plate in which a wafer stacked cylindrical body is adhered to the support plate and a cut is made for cutting into stacked chips, and FIG. 7 is a perspective view of a conventional stacked chip. in,
FIG. 7(a) shows an example of a product with a good shape, and FIGS. 7(b) and (C) each show an example of a product with a defective shape. 1 Semiconductor wafer, 2 Support plate, 3 Wafer Fig. 2 Fig. 3 Concave Fig. 4 Fig. 6 (Q) (b) CC) Fig. 7
Claims (1)
層接着したウェハー積層円柱体の一主面を支持板の面に
接着し、前記半導体ウェハーまたはウェハー積層円柱体
を所定の寸法形状に切断してチップとするダイオードチ
ップの製造方法において、一面に半導体ウェハーの外径
より所定量だけ小径でかつその幅がダイオードチップの
外接円の直径より若干広いリング状の溝を有する支持板
を用い、該支持板の他面に半導体ウェハーまたはウェハ
ー積層円柱体の一面を前記リング状の溝と同心に接着し
、該半導体ウェハーまたはウェハー積層円柱体を所定の
寸法形状に切断するとき前記支持板のウェハー接着面に
まで切り込み、その切り込み深さは少なくとも前記支持
板のウェハー接着面の反対面に設けられた前記リング状
の溝の底にまで達していることを特徴とするダイオード
チップの製造方法。1) One main surface of a semiconductor wafer or a wafer-stacked cylindrical body obtained by laminating and bonding a plurality of semiconductor wafers is adhered to the surface of a support plate, and the semiconductor wafer or wafer-stacked cylindrical body is cut into predetermined dimensions and shapes to form chips. In a method for manufacturing a diode chip, a support plate having a ring-shaped groove on one side having a diameter smaller than the outer diameter of a semiconductor wafer by a predetermined amount and whose width is slightly wider than the diameter of the circumscribed circle of the diode chip is used, and the support plate is One side of the semiconductor wafer or wafer stacked cylinder is adhered to the other surface concentrically with the ring-shaped groove, and when the semiconductor wafer or wafer stacked cylinder is cut into a predetermined size and shape, the wafer bonding surface of the support plate is covered. A method for manufacturing a diode chip, characterized in that the depth of the cut reaches at least the bottom of the ring-shaped groove provided on the opposite surface of the support plate to the wafer bonding surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9667587A JPS63261869A (en) | 1987-04-20 | 1987-04-20 | Manufacture of diode chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9667587A JPS63261869A (en) | 1987-04-20 | 1987-04-20 | Manufacture of diode chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63261869A true JPS63261869A (en) | 1988-10-28 |
Family
ID=14171371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9667587A Pending JPS63261869A (en) | 1987-04-20 | 1987-04-20 | Manufacture of diode chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63261869A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09506797A (en) * | 1993-12-22 | 1997-07-08 | エイ． レディンハム，ブレイク | Painting brush with replaceable bristle pack |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60170959A (en) * | 1984-02-16 | 1985-09-04 | Fuji Electric Co Ltd | Manufacture of diode chip |
-
1987
- 1987-04-20 JP JP9667587A patent/JPS63261869A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60170959A (en) * | 1984-02-16 | 1985-09-04 | Fuji Electric Co Ltd | Manufacture of diode chip |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09506797A (en) * | 1993-12-22 | 1997-07-08 | エイ． レディンハム，ブレイク | Painting brush with replaceable bristle pack |
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