JPS63248175A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To scale down the cell size, and to reduce the occupying area of a storage element by forming a floating gate onto the same plane, surrounding a control gate in a floating gate type EEPROM semiconductor device. CONSTITUTION:A control gate 7 is shaped into a specified region in an insulating film 4 formed onto a semiconductor substrate 1, and a floating gate 5 is shaped onto the same plane, surrounding the gate 7, thus forming an EEPROM. According to the gate constitution, even when the area of a cell is reduced, the area of the floating gate is increased, thus scaling down the size of the cell, then diminishing the occupying area of a storage element.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor memory devices, and in particular to nonvolatile memories in which information can be electrically written and erased, so-called E
E P ROM (E Electrically E
rasable and Proara+uabl
e Read Qnly Memory)
This relates to the structure of a memory element.

[Prior Art] FIGS. 2A to 2C are diagrams showing the structure of a conventional floating gate type semiconductor memory device (EEPROM).

FIG. 2A is a plan view showing the arrangement of semiconductor memory elements;
FIG. 2B is a sectional view taken along A-AI in FIG. 2A,
FIG. 2C is a sectional view taken along B-all in FIG. 2A. The configuration of a conventional semiconductor memory device will be described below with reference to FIGS. 2A to 2C.

In the figure, a source region 22 and a drain region 23 made of impurity diffusion layers are formed on the surface of a semiconductor substrate 21 at a predetermined interval. An insulating film (oxide film) 24 is formed on the source region 22, drain region 23 and the surface of the semiconductor substrate 21, and a predetermined region of the insulating film 24 on the drain region 23 is formed to a thin m thickness to form a tunnel. It is said to be oxidized 11!24a. A floating gate 25 made of polysilicon is formed in a region on the insulating film 24 that includes at least the tunnel oxide fl 124a. Further, a control gate 27 is placed on the floating gate 25 via an interlayer insulator [126].
is formed.

The source region 22, drain region 23, tunnel oxide film 24a1 floating gate 25, and control gate 27 constitute the successive transistor TR1. Note that a portion of the floating gate 25 located on the region between the source region 22 and the drain region 23 serves as a gate region 25a of the read transistor TRI.

The control gate 27 and the floating gate 25 form a capacitance in the overlapping region using the interlayer insulating film 2G between them as a dielectric material. Furthermore, the floating gate 25 and the drain region 23 form a capacitance in the region where the tunnel oxide 124a is formed, using the tunnel oxide 11124a as a dielectric material. Furthermore, in the region excluding tunnel oxidation 1!24a, )O-
There is also a capacitance formed by the ting gate 25 and the semiconductor substrate 21.

Floating gate 25 stores charge, and discharges and injects charge between control gate 27 and drain region 23 via tunnel oxide 11124a depending on the voltage applied between control gate 27 and drain region 23.
□ On the other hand, the drain region 2 is formed on the surface of the semiconductor substrate 21.
3 and another drain region 2 are formed at a predetermined interval. A word line 29 receiving a selection signal is formed on the insulator 1124, and a portion of the word line 29 located on a region between the drain region 23 and the other drain region 28 is This is a gate region 29a.

The above drain region 23, drain region 28, and gate region 29a constitute the selection transistor TR2, and in this case, the drain region 23 is used as a source region. That is, the drain region 23 of the read transistor TR1 also serves as the source region of the selection transistor TR2. The train region 28 is connected via a contact hole 30 to a bit line 31 made of an aluminum wiring layer. The selection transistor R2 is
A successive transistor TR connected thereto turns on and off in response to a signal applied via the word line 29.
1 is read out to the pit line 31.

Further, adjacent memory elements are electrically insulated by the M region 32 corresponding to the element size.

FIG. 3 is a diagram showing an equivalent circuit of the semiconductor memory element shown in FIGS. 2A to 2C. In figure M3, the drain D of the read transistor TR1 and the source of the selection transistor TR2 are formed of the same diffusion layer 23 and are connected to each other.

Further, as described above, in the read transistor TR1, the control gate 27 and the 70-ting gate 2
5 and the semiconductor substrate 21 are each formed with an insulating film interposed therebetween, so that a capacitance is formed between them to form a capacitive circuit.

FIG. 4 is a diagram showing an equivalent circuit of a capacitive circuit constituted by the read transistor TR1. In FIG. 4, a capacitor 133 is formed by the control gate 27, the interlayer insulating film 26, and the 70-ring gate 25, and the floating gate 25, the tunnel oxide film 24a, and the drain region 23 are formed.
A capacitor 34 is formed by these. A capacitor 135 is formed by removing each of the capacitors 134 from the capacitor formed between the floating gate 25 and the semiconductor substrate 21. The capacitor ff134 and the capacitor 35 are electrically connected in parallel, and the capacitor 33 is electrically connected in series to this parallel body.

The operation of the semiconductor memory element will be described below with reference to FIGS. 2A to 2C, FIGS. 3 and 4.

This type of floating gate type semiconductor memory element is
Information is stored depending on whether an excessive amount of electrons is accumulated in the FOT ink gate 25, or whether there is a shortage of electrons and an apparent high charge exists.

The operation of injecting electrons into the 70-ring gate 25 is as follows. First, a program voltage VpP is applied to the word line 29 (WL) and the control gate 27 (CG>), and the bit line 31 (BL) and the source region 22 (S) of the read transistor TR1 are brought to the ground potential (OV). .

At this time, an inversion layer is formed on the surface of the semiconductor substrate 21 below the word line 29, and the inversion layer and the selection transistor T
Through the drain 28 of R2, the read transistor TR
The drain region of I (i.e., the selection transistor TR
The potential of the source m1d) 23 (D) of bit line 3
The ground potential (OV) is the same as 1.

Figure 5 shows the successive output transistor TRI during electron injection.
FIG.

As shown in FIG. 5, the control gate 27 (
CG), a program voltage VPP is applied to the source region 1
jt22(S)a and drain region 23(D) are grounded. At this time, the semiconductor substrate 21 is always grounded. The charge Q" is the charge accumulated in the floating gate 25, and the voltage V" is the charge accumulated in the floating gate 25.
The capacitance formed by ff131 is the applied voltage.

Now, the capacity value of capacity 34 is CI, and the capacity value of W quantity 33 is 02
, the capacitance value of the capacitor 35 is 03, then the voltage V is approximately as follows: Vr = (C2・Vrp −QF )/Cy・” (1)
It is expressed as Here, Cr-C1+C2+C3.

The voltage Vr expressed by the above equation (1) is applied to the thin tunnel oxide film 24a, and a high electric field is applied thereto.

This causes the drain region 23 to have l! j: tE-f electrons move through the tunnel oxide film region Fowler -N ord
The current flows as a heiIll type tunnel current and is accumulated in the floating gate 25.

On the other hand, when extracting electrons from the floating gate 25, a program voltage VtP is applied to the word line 29 (WL>) and the pit line 31 (BL), and the control gate 27 (CG) is set to the ground potential (OV). Source region 22 of transistor TR1 (
S) is electrically brought into a 70-ting state to prevent electrons from flowing out from there. At this time, the selection transistor TR2 becomes conductive, and the read transistor TR1
The potential of the drain region (that is, the source region of the selection transistor TR2>23 (D)) is approximately the same as the potential VPP of the pit line 31.

Figure 6 shows the successive output transistor TR when extracting electrons.
FIG. 2 is a diagram showing an equivalent circuit of a capacitor circuit configured by I. 6th
As shown in the figure, since the semiconductor substrate 21 is grounded, the source region 22 is electrically floating.
(S) is grounded via the semiconductor substrate 21. Further, since the programming voltage VPP is applied to the drain a region 23 (D) and the semiconductor substrate 21 is grounded, a junction capacitance is formed between them, and this junction capacitance is capacitance! 135, and its capacitance value becomes C3'.

However, approximately, this junction capacitance is small and approximately equal to the capacitance value C3 at the time of electron injection. Therefore, the voltage Vy applied to the capacitor 34 is:

Vr - ((C2+03')VFF -Qr)/
(C1+02+03')...(2) is expressed. Voltage VF expressed by the above equation (2) is applied to tunnel oxide 1124a to apply a high electric field. As a result, the electrons in the floating gate 25 become F o
Flows into the drain region 23 as a wler-N ordhela type tunnel current, and flows into the floating gate 25.
There is a lack of electrons within.

When there are excessive electrons in the floating gate 25, the threshold voltage of the successive transistor TR1 increases,
The continuous current becomes smaller. On the contrary, floating gate 2
When electrons in the transistor 5 become insufficient, the threshold voltage of the successive output transistor TRI decreases, and the successive output current increases. The magnitude of this read current is stored in correspondence with digital information "0" and "17".

[Problems to be solved by the invention] A conventional semiconductor memory device is configured as described above.
Tunnel oxidation 11 in order to store information in the storage element
Electrons are exchanged by applying a high electric field to 124a and causing a tunnel current to flow between the 70-ring gate 25 and the drain region 23 of the successive transistor TR1. Here, as seen from the previous equations (1) and (2), in order to generate the tunnel N flow, the tunnel oxide film 2
In order to increase the electric current applied to 4a, (1) reduce the area of the tunnel oxide film 24a region, (11) thin the interlayer insulating film between the floating gate 25 and the control gate 27, (Ili )70-It is necessary to increase the overlapping area of the gate 25 and the control gate 27.

However, in the case of (1), it is extremely difficult to reduce the area of the tunnel oxide 111248 region to 1 μm2 or less because it is close to the performance limit of the manufacturing equipment, and in the case of (11), there is a possibility that the data retention characteristics will deteriorate. In the case of (Ili,), the cell area increases, going against the direction of high integration.

In addition, as shown in FIGS. 2A to 2C, the tunnel region, the successive transistor section, and the selection transistor section are each formed in separate regions without overlapping in plan view. However, the conventional structure of a memory element has problems such as difficulty in miniaturizing the memory element.

Therefore, an object of the present invention is to provide a semiconductor memory device that can solve the above-mentioned problems, reduce the area occupied by the memory element, and further reduce the program voltage VFF. be.

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a first semiconductor memory device on a semiconductor substrate.
An insulating film is formed, and a control gate is formed in a predetermined region on this first insulating film. and said first control gate at least partially surrounding said control gate.
A floating gate is formed on the insulating film region of
Further, a second insulating film is formed between the control gate and the floating gate.

[Function] In the semiconductor memory device according to the present invention, since the floating gate is formed on the same plane so as to at least partially surround the control gate, the area of the floating gate is reduced. therefore,
The cell size can be reduced, and the area occupied by the memory element can be reduced.

Examples] Hereinafter, a practical example of this invention will be explained using the drawings.

1A and 1B show a semiconductor memory device which is an example of the present invention, in which FIG. 1A is a plan view and FIG. 1B is a sectional view taken along the line XX of FIG. 1A.

In the figure, a source region 2 and a drain region 3 made of impurity diffusion layers are formed in a predetermined region on the surface of a semiconductor substrate 1 at a predetermined interval.

An insulating film (oxide film) 4 is formed on the source region 2, drain region 3, and the surface of the semiconductor plate 1. A predetermined portion of this insulation l1lI4 located on the drain region 3 is formed to have a thinner film thickness than other portions, resulting in tunnel oxidation! It is said to be ll4a.

A control gate 7 is formed on the insulating film 4 in the region between the source region 2 and the drain region 3. A U-shaped 70-ting gate 5 made of polysilicon is formed on a region surrounding the control gate 7 and including the tunnel oxide 114a. Between this 70-ting gate 5 and the control gate 7, there is a layer gap of 1tl! 6 is formed.

Above source region 2, drain region 3, tunnel oxide 1
14a, the floating gate 5, and the control gate 7 constitute the successive output transistor TR1. Note that) the source region 2 of the O-ting gate 5
A portion located on the region between the gate region 3 and the drain region 3 serves as the gate region 5a of the read transistor TR1.

The control gate 7 and floating gate 5 are
A capacitor is formed using the interlayer insulation 116 as a dielectric material. In addition, the floating gate 5 and the drain region 3
That is, a capacitor is formed using the insulating film 4 including the tunnel oxide 114a as a dielectric material. In general, there is also a capacitance formed by the floating gate 5 and the semiconductor substrate 1.

Floating gate 5 stores charge, and releases and injects charge between control gate 7 and drain region 3 via tunnel oxide 114a depending on the voltage applied between control gate 7 and drain region 3.

On the other hand, another train region 8 is formed on the surface of the semiconductor substrate 1 at a predetermined distance from the drain region 3. A word line 9 receiving a selection signal is formed on the line Rm4, and among this word line 9,
A portion above the region between the drain region 3 and the other drain region 8 serves as a gate region 9a.

The above drain region [3, drain region 8, and gate region 9a constitute a selection transistor TR2,
In this case, the drain region 3 is used as a source region. That is, the drain region 3 of the successive transistor TRI also serves as the source region of the selection transistor TR2. Drain region 8 is connected via contact hole 10 to pit line 11 made of an aluminum wiring layer.

This selection transistor TR2 has a feature that the source region 2 of the successive transistor TR1 and the inversion layer generated by the electric field of the O-ting gate 5 are combined as a source region. This selection transistor TR2 is turned on and off in response to a signal applied via the word line 9, and is connected to the successive transistor TRI.
The information contained in the bit line 11 is read out to the bit line 11.

Note that adjacent memory elements 100 are electrically insulated by an inter-element isolation region (not shown).

The operation of this semiconductor memory device is similar to the operation of the semiconductor memory device shown in the prior art.

That is, when electrons are injected into the floating gate 5, the program voltage VPr is applied to the word line 9 and the control gate 7, and the pit line 11 and the source region 2 of the read transistor TR1 are set to the ground potential (Ov). A voltage VF expressed by the above-mentioned equation (1) is applied to the thin tunnel oxide 114a to apply a high electric field.

As a result, electrons existing in the drain region 3 flow through the tunnel oxide 1!4a as a tunnel current and are accumulated in the floating gate 5.

Furthermore, when extracting electrons from the floating gate 5, the program voltage VPP is applied to the word line 9 and the bit line 11, the control gate 7 is brought to the ground potential (OV), and the source region 2 is brought into a floating state. Voltage V expressed by equation (2)
r is applied to tunnel oxide 114a and a high electric field is applied. As a result, electrons in the floating gate 5 flow to the drain region 3 as a tunnel current, thereby depleting the electrons in the floating gate 5.

In this semiconductor memory device, the floating gate 5 is formed on the same plane in a square shape so as to surround the control gate, so the area of the floating gate 5 is large.Therefore, the cell size It is possible to reduce the area occupied by the memory element.Furthermore, the floating gate 5
Since the area of V increases, the electric field applied to the tunnel oxide film 4a increases, and thereby
FP can be reduced.

Furthermore, since the floating gate 5 and the control gate 7 are formed on the same plane, the manufacturing process is facilitated.

In the above embodiment, the insulating film 4b between the source region 2 and the floating gate 5a is formed in the same way as the tunnel oxide film 4a, but this insulating film m4b is formed in the same way as the insulating film y44 in other regions or It may be formed thickly.

[Effects of the Invention] As described above, according to the present invention, since the floating gate is formed so as to at least partially surround the control gate, even if the cell area is reduced, it is possible to Since the area of * is large, integration can be achieved and the programming voltage can be reduced. Furthermore, since the floating gate and the control gate are formed on the same plane, the manufacturing process is facilitated. Therefore, high integration, high capacity semiconductor record 1! It becomes possible to realize the device.

[Brief explanation of drawings]

FIG. 1A is a plan view showing a practical example of a semiconductor memory device according to the present invention, FIG. 1B is a sectional view taken along the line X--X of FIG. 1A, and FIG. Figure 2B is a sectional view taken along line A-A in Figure 2A, and Figure 2C is a cross-sectional view taken along line 5 in Figure 2A.
-Sa sectional view, Fig. 3 is a diagram showing an equivalent circuit of a semiconductor memory element, Fig. 4 is a diagram showing an equivalent circuit of a capacitive circuit constituted by successive transistors, and Fig. 5 is a diagram showing an equivalent circuit of a capacitive circuit when electrons are injected. FIG. 6 is a diagram showing an equivalent circuit of a capacitance port and a path when electrons are emitted. In the figure, 1 is a semiconductor substrate and 2 is a source region. 3 is a drain region, 4 is an insulating film, 4a is a tunnel oxide film, 5 is a floating gate, 5a is a gate region, 6 is an interlayer insulation layer, and 7 is a control gate. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (5)

[Claims] (1) a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a control gate formed in a predetermined region on the first insulating film; and a control gate that at least partially surrounds the control. 1st
a floating gate formed in a region on an insulating film; and a second insulating film formed between the control gate and the floating gate, and by applying a predetermined voltage to the control gate, A semiconductor memory device in which the charge accumulation operation of a floating gate is controlled. (2) At least a partial region of the first insulating film under the floating gate is provided with a tunnel region that is thinner than other regions. The semiconductor storage device described above. (3) The semiconductor memory device according to claim 2, wherein the tunnel region has a film thickness of 200 Å or less. (4) An impurity diffusion region is formed in a predetermined region of the surface of the semiconductor substrate, and at least a part of the tunnel region is located on the impurity diffusion region. 3. The semiconductor memory device according to item 3. (5) Impurity diffusion regions serving as a source and drain are formed in predetermined regions on the surface of the semiconductor substrate, and a portion of the floating gate is located on a region between the impurity diffusion regions and also serves as a gate region. A semiconductor memory device according to any one of claims 1 to 4.