JPS6324644A - Method for formation of multilayer structure - Google Patents

Method for formation of multilayer structure

Info

Publication number
JPS6324644A
JPS6324644A JP16851886A JP16851886A JPS6324644A JP S6324644 A JPS6324644 A JP S6324644A JP 16851886 A JP16851886 A JP 16851886A JP 16851886 A JP16851886 A JP 16851886A JP S6324644 A JPS6324644 A JP S6324644A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
layer
formed
si layer
si
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16851886A
Inventor
Shuichi Harajiri
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

PURPOSE: To prevent the deterioration in withstand voltage by a method wherein an oxide film is formed on the surface of an amorphous Si layer or a polycrystalline Si layer, and a polysilicon Si layer is formed on said oxide film.
CONSTITUTION: A highly doped polysilicon Si layer 2 and an a-Si layer 3 are formed on the gate insulating layer 1A formed on a substrate 1 as the first layer of conductive layer. Then, an SiO2 layer 4 is formed by thermally oxidizing the surface of the a-Si layer 3 which will be turned into an interlayer insulating layer. A highly doped polysilicon Si layer 5 is formed on the SiO2 layer 4 as the second layer of conductive layer. As above-mentioned, the first conductive layer is formed first and the a-Si layer of small grain size or an undoped polysilicon Si layer is formed on the first conductive layer after the heat treatment such as a doping and the like bas been finished, and as the polysilicon Si is recrystallized and grains are not grown by forming the interlayer insulating layer by thermally oxidizing the Si layer, the deterioration in withstand voltage of the title multilayer structure can be prevented.
COPYRIGHT: (C)1988,JPO&Japio
JP16851886A 1986-07-17 1986-07-17 Method for formation of multilayer structure Pending JPS6324644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16851886A JPS6324644A (en) 1986-07-17 1986-07-17 Method for formation of multilayer structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16851886A JPS6324644A (en) 1986-07-17 1986-07-17 Method for formation of multilayer structure

Publications (1)

Publication Number Publication Date
JPS6324644A true true JPS6324644A (en) 1988-02-02

Family

ID=15869518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16851886A Pending JPS6324644A (en) 1986-07-17 1986-07-17 Method for formation of multilayer structure

Country Status (1)

Country Link
JP (1) JPS6324644A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6144062A (en) * 1997-03-19 2000-11-07 Hitachi, Ltd. Semiconductor device having thin electrode layer adjacent gate insulator and method of manufacture

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6144062A (en) * 1997-03-19 2000-11-07 Hitachi, Ltd. Semiconductor device having thin electrode layer adjacent gate insulator and method of manufacture
US6521943B1 (en) 1997-03-19 2003-02-18 Hitachi, Ltd. Semiconductor device having thin electrode layer adjacent gate insulator and method of manufacture
US6723625B2 (en) 1997-03-19 2004-04-20 Renesas Technology Corporation Semiconductor device having thin electrode laye adjacent gate insulator and method of manufacture

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