JPS63245119A - Buffer circuit - Google Patents

Buffer circuit

Info

Publication number
JPS63245119A
JPS63245119A JP62079932A JP7993287A JPS63245119A JP S63245119 A JPS63245119 A JP S63245119A JP 62079932 A JP62079932 A JP 62079932A JP 7993287 A JP7993287 A JP 7993287A JP S63245119 A JPS63245119 A JP S63245119A
Authority
JP
Japan
Prior art keywords
dimension
tr
receiving
channel
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62079932A
Inventor
Yuji Kihara
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62079932A priority Critical patent/JPS63245119A/en
Publication of JPS63245119A publication Critical patent/JPS63245119A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To attain high speed access by connecting plural buffer circuits of plural stages of constitution in parallel and making logical threshold values of each 1st stage buffer of the plural buffer circuits receiving a signal to be subject to buffering differ from each other.
CONSTITUTION: The dimension of a P-channel transistor (TR) 1 in an inverter P1 of the 1st stage buffer receiving an RD signal to be buffered is made larger than the dimension of the N-channel TR 2 and the dimension of the N-channel TR 6 of the inverter P2 of the 1st-stage buffer is increased more than the dimension of the P-channel TR 5 similarly. In receiving the RD signal on a read data bus RD, a data output DO reaches the state equalized once into an intermediate level earlier than the output of the normal data. Thus, high speed access is attained.
COPYRIGHT: (C)1988,JPO&Japio
JP62079932A 1987-03-31 1987-03-31 Buffer circuit Pending JPS63245119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62079932A JPS63245119A (en) 1987-03-31 1987-03-31 Buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62079932A JPS63245119A (en) 1987-03-31 1987-03-31 Buffer circuit

Publications (1)

Publication Number Publication Date
JPS63245119A true JPS63245119A (en) 1988-10-12

Family

ID=13704087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62079932A Pending JPS63245119A (en) 1987-03-31 1987-03-31 Buffer circuit

Country Status (1)

Country Link
JP (1) JPS63245119A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5739715A (en) * 1995-10-31 1998-04-14 Hewlett-Packard Co. Digital signal driver circuit having a high slew rate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5739715A (en) * 1995-10-31 1998-04-14 Hewlett-Packard Co. Digital signal driver circuit having a high slew rate

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