JPS63243888A - Wiring inspection device - Google Patents

Abstract

PURPOSE:To perform high-speed inspection by inspecting a short circuit by using connection data held in 1st and 2nd data holding means and inspecting the disconnection of a wire by using the inverted data of connection data held in a 3rd data holding means. CONSTITUTION:When, for example, the short-circuit inspection is performed, a signal SH is held at a H level and a switch 11 is selected so that the output of an addressable latch 8 is selected. Then a microprocessor MPU reads connection data out of a RAM 1 and starts inspection. Here, data 0001 is decoded and latched in addressable latches 7 and 9. Therefore, an inspection point P1 is stored in the latches 7 and 9 and a drive switch S1 is turned on with the output of the latch 7. Then an inspection point P5 is stored newly in latches 8 and 9 and two inspection points P1 and P5 are held at the H level in the latch 9. The output of the latch 8 is passed through the switch 11 to turn on a sense switch SW5, and then a current flows in the order of a constant voltage source 14, a constant current source 13, a switch D1, the inspection point P1, a printed board, the inspection point P5, the switch SW5, a current detector 16, and the power source 14, so that it is known that the circuit is normal.

Description

[Detailed Description of the Invention] [Structure of the Invention] (Industrial Application Field) The present invention is a wiring inspection device for inspecting the electrical connection state of wiring of a printed wiring board or the like formed with a plurality of conductive patterns. Regarding.

(Conventional technology) The inspection method of this type of wiring inspection device is as follows.

That is, for example, when attempting to inspect a short circuit (short circuit) or disconnection #I (open) of an IL conductive pattern on a printed wiring board, a power supply is connected between two appropriate points of the conductive pattern, and the continuity between these two points is checked. / Check for non-continuity. here,
When there is continuity, it is determined that the circuit is normal, and when there is no conduction, it is determined that there is an abnormality, that is, a disconnection. In addition, the short circuit test is performed as follows. That is, a power source is connected to appropriate positions of two or more conductive patterns that are not normally electrically connected, and continuity/non-continuity between these two points is checked. Here, when there is no conduction, it is determined that it is normal, and when there is 4 connections, it is determined that there is an abnormality, that is, a short circuit.

The apparatus configuration for implementing such a method is as follows. That is, in order to perform the above-mentioned inspection method on a large number of patterns, a microprocessor used in a computer, a sequence controller, etc., and a memory that stores a plurality of conductive patterns of the print to be inspected 13 (fQ) as connection data are used. , the connection data is retrieved one by one from this memory, and this data is used to connect a contactor for conduction between two appropriate points of one conductive pattern or between two or more appropriate points of each of two or more conductive patterns. The N source is connected to the probe bin and its continuity/non-continuity is checked.

In such a configuration, it is necessary to connect a power supply between one reference conductive pattern and many other conductive patterns, and it is also necessary to connect a power supply between one reference conductive pattern and many other conductive patterns, and it is also necessary to connect a power supply between one reference conductive pattern and a number of other conductive patterns. In the test, continuity indicates normality, which is a contradictory matter, so signal processing is also required for this judgment.For this reason, when testing for short circuits, the connection data for short circuit tests is stored in memory, and the short circuit test data is stored in memory. This requires a two-step process of executing the test, storing the connection data for disconnection test in memory, and executing the disconnection test after completing the test, which is contrary to the automation and high speed required for this type of test equipment. It was a problem.

(Problems to be Solved by the Invention) According to the conventional technology, a two-step process is required to perform short circuit inspection and spot inspection, and the automatic Moreover, it was contrary to high speed performance, which was a problem.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a wiring inspection device that can automatically and quickly perform short circuit inspection and disconnection inspection.

[Ili of the Invention] (Means for Solving the Problems) In order to solve the above problems and achieve the object, the present invention has a configuration in which the following means are taken. That is, the present invention provides a wiring inspection device for inspecting the electrical connection state of wiring such as a printed wiring board formed with a plurality of conductive patterns, in which a drive switch and a detection switch are connected in series, and this connection line is connected in series. A plurality of inspection line elements that electrically contact the conductive pattern of the wiring to be inspected, and a current flowing through two or more of the plurality of inspection line elements to determine whether the current is flowing or not. a detection means for detecting a short circuit or a disconnection between the drive switches; a first data holding means for holding data for driving the drive switch to open and close; and a second data holding means for holding data for driving the drive switch to open and close. a holding means, a third data holding means for holding data for driving the detection switch to open and close, and an inspection data storage means for storing a plurality of conductive patterns of the wiring to be inspected as connection data for each address;
The connection data from the test data storage means is sequentially applied to the first data storage means and the second data storage means to execute a short circuit test, and the connection data from the test data storage means is applied to the second data storage means. The third data holding means supplies data to the test switch in an inverted manner so as to execute a disconnection test.

(Function) According to such a configuration, the first. The connection data held in the second data holding means can be used to drive the test line element to perform a short circuit test, and the connection data held in the third data holding means can then be inverted and used to drive the test line element. By driving , it becomes possible to perform a disconnection inspection.

(Embodiment) The configuration of an embodiment of the wiring inspection device according to the present invention will be described below with reference to FIG.

In FIG. 1, a microprocessor MPU operates the apparatus by reading a control program written in a ROM (not shown) and executing its control contents.

RAM1 contains 1! of the printed circuit board to be inspected. Connection data indicating electrical patterns is stored, for example, in a table format as shown in FIG. The connection data is read from the RAM 1 in response to a read signal RD from the microprocessor MPU, and is output to the data bus DB. Note that the read signal RD is outputted only when only an address is accessed in the layout of the RAM 1.

When the drive point selection signal DV is at H level, the read signal @RD is also input to the drive addressable latch D7 through the AND circuit 2, that is, the RAMI connection data is held in the drive addressable latch D7. . Also, the sense exclusion addressable latch XS9 includes an AND circuit 4°OR circuit 5. Since the read signal RD is input through the AND circuit 6, the connection data of the RAM1 is held in the sense exclusion addressable latch XS9.

When the sense point selection signal SS is at H level, the sense addressable latch D7.88 is
The connection data of RAM1 is held in . Further, when the sense exclusion point selection signal @xSS is at H level, the connection data of the RAMI is held only in the sense exclusion addressable latch XS9.

The output of the drive latch D7 is used as a drive selection signal to drive each of the drive switches D1 to D12 via the drive section 10. Addressable latch 38
．． In XS9, the switch 11 is switched by the short circuit inspection/disconnection inspection switching signal SH, and in this case, the addressable latch
The data from S9 is inverted by the inverting element 9a and drives each of the sense switches SW1 to SW12 via the driving section 11. Current detector 15, 16゜1
7 indicates drive switches D1 to D12, a 1m pattern of the printed circuit board to be inspected, and sense switches SW1 to 5W12.
The current flowing through the current is detected and it is determined whether the current is equal to or higher than the determination level. The outputs of the current detectors 15, 16, and 17 are selected by the select signal SEL and input to the OR circuit 21 through the output switches 18, 19, and 20.

The output of the OR circuit 21 is input to the microprocessor MPU, and is configured to notify the microprocessor MPU of current detection.

Output switches 18, 19, and 20 are always on during normal testing and monitor all detection systems.

The inspection points P1 to P12 are connected to the check points of each conductive pattern of the home printed cover board to be inspected by probe bins.

The constant voltage power supply 14 supplies voltage to the switching circuit, and the constant currents 12 and 13 are inserted in series to suppress excessive current.

Figure 2 is an example of the contents of the standard data in RAMI, and 1
This is a hexadecimal representation of a 0-decimal number.

Furthermore, the value FFFF represents the end of the connection as a value that does not physically exist in the switching circuit. Also,
If FFFF is compared twice in a row, it means that all inspection points have been completed.

Therefore, the example data in FIG. 2 has a pattern as shown in FIG. 3.

Next, the operation of this embodiment configured as described above will be explained with reference to the flowchart shown in FIG. Starts in step S1, sets address AD to 0 in step S2, and clears signals XCL, DCL, SC' in steps 83 and 84.
Exit L and address latch D7. S8. Clear the output of XS9.

As a result, each switching element D1 to D12, SWI
~5W12 is in the off state.

Further, in step S5, the process moves to a short circuit test. That is,
The switch 11 is selected by setting the signal @SH to H level so that the output of the addressable latch S8 is selected. Next, the microprocessor MPU reads the connection data in RAM1 and starts checking, but the beginning of the table in RAM1 is
Since this is the drive point, that is, the beginning of the pattern, the DV-1 level, 5S-L level, and X5S-L level are set so that the data at address 0 of RAM1 is sent to the drive latch D7 as step S6. Here, step $7
When data is read at address 0, the contents of address 0001 are transferred to addressable latch D7. Decoded and latched within XSQ.

Therefore, inspection point P1 is stored in latch D7 and XS9,
The output of the latch D7 turns the drive switch D1 on. At the same time, the processor MPU reads the data on the data bus and saves it to the internal register, and in steps S8 and 89, the contents of address 0 of RAM1 are set to FF.
You can confirm that it is not FF. Therefore, the next test point will be the point connected to Pl, so the processor M
The PIJ sends the RAMI address data to the addressable latch S8, and executes steps $10 to 816 below.

First, the DV-L level, the 8S-H level, and the X5S-L level are assumed. Now, when this data is read, the contents of address 1, that is, the data 0005, will be transferred to the addressable latch S.
8. Decoded and latched within XSQ. Therefore,
Test point P5 is newly stored in latches S8 and XS9.

Since the inspection point P1 is also stored in the latch XSQ, the two points PI and P5 are in the stored state (H level).

The output of the addressable latch $8 turns on the sense switch SW5 through the switch 11, so if the pattern of the printed circuit board to be inspected is connected normally, 14→
13 → D1 → P1 → Print base temporary → P5 → SW5 → 16
→You can see that current flows through path 14 and the circuit is connected.

If there is a break in the pattern at this point, no current detector output will be obtained, so it can be determined that P1 and P5 stored in the processor internal register are broken.

Furthermore, since the processor MPU can confirm that the content at address 1 is not FFFF, it outputs the sense clear SCL in step S11 to clear the content of the addressable latch S8, that is, turn off SW5.

Similarly, in step 812, the value of the address AD is increased to addresses 2, 3, and 4, and it is checked whether P5, P8, pH, and Pl2 to which the drive point P1 is connected are connected.

In step 813, when the address AD is further set to address 5 and data is read, the addressable latch S8 has an FF
FF data is input, but since such a large point does not physically exist, the addressable latch S
There is no change in the memory contents of 8. That is, latch D7 is PI, latch S8 is nothing, and latch XS9 is PI, P.
5, P8.

Pll and Pl2 are at H level. ) At this point processor MPLI reads FFFF and steps 8
Since it is found in step S14 that the connection test for one pattern has been completed, the switch 11 is selected in step S14 to select the addressable latch XS9 for the disconnection test (that is, the 5H-L level). , the contents of latch XS9 are Pl , P5 , P8 , Pll
, Pl2 is at H level, but its output is inverted, so P2, P3.

P4. P6. P7. P9. All sense switches of Plo are turned on at the same time. Then, in step 812, the first patterns pi, ps, pa, pli are created.

If Pl2 is insulated from other patterns, the processor input line fNT remains at the L level due to the outputs of the current detectors A115 to A317 in step 819.
This means that the inspection of the first pattern has been completed.

In this manner, according to this embodiment, the disconnection test can be performed subsequent to the short circuit test, so that the test can be performed automatically and at high speed.

Furthermore, since a single connection cable is required between the switching circuit required for inspection and the processor side, this is advantageous in terms of program size, etc.

Furthermore, reading of RAM data of the processor MPtJ and writing of drive points and sense points can be performed at the same timing, so there is no waste.

Furthermore, since the drive point and sense point are written in the sense exclusion addressable latch XS9 in the short-circuit test, it is advantageous that the test can be performed at once by using the inverted data in the disconnection test.

The present invention has the following modifications.

The inspection points shown in FIG. 1 are not limiting. Further, the same function may be obtained by using a decoder and a latch instead of the addressable latch.

Further, although RAM is used for storing connection data, ROM or the like may also be used.

The invention can be modified in various ways without departing from the gist of the invention.

[Effects of the Invention] As described above, the present invention includes a plurality of inspection line elements in which a drive switch and a detection switch are connected in series, and the connection line is electrically contacted with the conductive pattern of the wiring to be inspected; Detection means for passing current through two or more of the plurality of inspection line elements to detect a short circuit or disconnection between the two or more inspection line elements based on the presence or absence of current, and data for driving the drive switch to open and close. a first data holding means for holding data for driving the detection switch to open and close; a second data holding means for holding data for driving the detection switch to open and close; and a third data holding means for holding data for driving the detection switch to open and close.
a data storage means, an inspection data storage means for storing a plurality of conductive patterns of the wiring to be inspected as connection data for each address, and a data storage means for sequentially transmitting connection data from the inspection data storage means to the first data storage means. The connection data from the test data storage means is supplied to the second data storage means to execute a short circuit test, and the third data storage means transmits the connection data from the third data storage means to the test switch. and a calculation means for performing a disconnection test by performing a reversal operation. Second
A short circuit test can be performed by driving the test line elements using the connection data held in the data holding means of the third data holding means.
It is now possible to perform a disconnection test by inverting the connection data held in the data holding means and driving the inspection line elements. Therefore, it is possible to perform short-circuit and disconnection tests automatically and at high speed. It is possible to provide a wiring inspection device that can perform the following operations.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the wiring inspection device according to the present invention, FIG. 2 is a diagram showing a table of connection data, FIG. 3 is a diagram showing inspection points in a conductive pattern, and FIG.
The figure is a flowchart showing the operation of this embodiment. MPU...Microprocessor, 1...RAM. 2.3.4...AND circuit, 5.12...OR circuit, 6...AND circuit, 7.8.9...Addressable latch o, s, xs. Applicant's agent Patent attorney Takehiko Suzue Figure 2■ Figure 3

Claims (1)

[Claims] In a wiring inspection device that inspects the electrical connection state of wiring such as a printed wiring board formed with a plurality of conductive patterns, a drive switch and a detection switch are connected in series, and this connection line is connected to the wiring of the wiring to be inspected. A plurality of inspection line elements that make electrical contact with a conductive pattern, and a current flowing through two or more of the plurality of inspection line elements to detect short circuits or disconnections between the two or more inspection line elements depending on whether or not the current is flowing. a detection means for detecting, a first data holding means for holding data for driving the drive switch to open and close, a second data holding means for holding data for driving the detection switch to open and close; a third data holding means that holds data for driving the switch to open and close;
inspection data storage means for storing a plurality of conductive patterns of the wiring to be inspected as connection data for each address; and connection data from the inspection data storage means are sequentially transferred to the first data storage means and the second data storage means. and the means to execute a short circuit test, and the connection data from the test data storage means is supplied to the second data holding means so that the third data holding means performs a reversing operation with respect to the test switch. 1. A wiring inspection device, comprising: arithmetic means for executing a wire breakage inspection based on a given value.