JPS63239857A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To apply a plurality of signals of different levels to the same terminal by connecting a control MISFET to wirings for connecting an external terminal to first and second circuits, turning the MISFET on when a first potential is supplied to the first circuit, and conducting the FET when a second potential is supplied to the second circuit. CONSTITUTION:An N-channel MISFETQM1 is provided between a pullup MISFETQP1 and wirings 11c at a terminal PAD (-RESET/Vpp), and controlled by control signals '1', '0', which are fed from a CPU. That is, when a resetter is used, '1' is delivered, and '0' is delivered at the time of writing Vpp of EPROM. The resetter REST is connected through a switch MISFETSW, the CPU, an arithmetic logic unit ALU to a circuit, such as a condition code register CCR, etc. A switch SW is closed when a terminal PAD is used as a reset terminal, i.e., when a semiconductor chip is reset. The switch SW is interrupted when the terminal PAD is used as a write terminal, i.e., when information of EPROM is written.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and is particularly applicable to a semiconductor integrated circuit device in which multiple types of signals with different levels are applied to one external terminal. It is effective.

[Prior art]

A microcomputer is now constructed on a single semiconductor chip. The external terminals (pins) for inputting, outputting, or inputting/outputting signals of this microcomputer are equipped with pull-up MISFETs consisting of P-channel MISFETs.
FET is connected. This means that the level of the input terminal of the microcomputer is fixed, and the N-channel MISFET of the terminal that outputs the signal from the N-channel MISFET is turned off.
This is to fix the output level when F is applied, or to delay the rise of the input voltage applied to the terminal when the power is turned on (to cause it to rise slowly) by adding a capacitor to the terminal. In addition, for pull-up MI 5FET, 1
For example, it is described in Hitachi 4-bit 1-chip microcomputer system, HMCS40 series, user's manual, March 1980 (4th edition), p. 117.

[Problem that the invention seeks to solve]

The inventor of the present invention discovered the first problem as a result of studying the pull-up MISFET consisting of the P-channel MISFET.

As microcomputers become more multifunctional, the number of external terminals (pins) is also increasing. Therefore, it may be possible to reduce the number of terminals by using one external terminal as a common terminal for two types of signals.

However, if the two types of signals have different potentials, for example, the microcomputer's reset signal and the EPROM (Electric
The potential levels of the signals used when writing/reading information in the llly programmable ROM are different. At this time, the high level (H) potential of the reset signal is approximately the power supply potential Vcc, for example, 5V, but the EPROM
The write potential VPP is, for example, 12.5V. For this reason, there is no problem when inputting a reset signal, but when writing data, a forward bias is created between the drain of the pull-up MISFET and the substrate or well region, which flows to the power supply side. Writing becomes impossible.

An object of the present invention is to provide a technique that allows a plurality of signals with different levels to be applied to the same terminal.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of one typical invention disclosed in this application is as follows.

That is, a control MISFET is connected to the wiring connecting the external terminal and the first circuit and the second circuit, and when supplying the first potential to the first circuit, the control MISFET
The ISFET is made conductive, and the control MISFET is made non-conductive when the second potential is supplied to the second circuit.

[Effect]

According to the above-mentioned means, since a signal with a potential higher than the power supply potential Vcc will not flow to the power supply side, a plurality of signals having different levels can be supplied from the same terminal.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of the vicinity of a bonding pad of a semiconductor device, FIG. 2 is a cross-sectional view taken along the line A-A in FIG. 1, and FIG. 3 is an equivalent circuit of the circuit shown in FIG. 1. . In addition, in order to make it easier to understand the structure on the semiconductor substrate, FIG.
Insulating films other than the field insulating film are not shown.

First, the configuration of the circuit will be explained using FIG.

In FIG. 3, terminal PAD is a bonding pad and serves as an input terminal of the circuit. OUT is the output terminal.

The wiring 11C extending from the terminal PAD is a P channel MI
S F E T Qpx and N channel MISF E
Internal circuit (inverter) I consisting of T Q u z
Connected to the input of N. A wiring 11E extending from the output terminal is connected to the output. N-channel MISFET
Q, , +7)''/-X is set to the ground potential Vss, for example, Ov.The source of the P-channel interlayer 5FET QP2 is set to the power supply potential Vcc, for example, 5V.

In this embodiment, an N-channel MISFET Q is provided between the P-channel Qp1 and the wiring 11°.

That is, the sources of N-channel MISFETQ, , are connected to wiring 11C, the sources of P-channel MISFETQ, , are connected to power supply potential Vcc, and
Q, , and P-channel MISFET Q, are connected. By connecting the gate electrode of P-channel MISFET Q7 to the ground potential Vss, a pull-up MISFET
It constitutes an FET.

The gate electrode of the N-channel MISFET Q, , is set to the N1" level or "
A control signal of OIt level is applied. signal'"
1'' is the high level, that is, the power supply potential Vcc level, and the signal 410 #l is the ground potential VsS level.

If the signal applied to the terminal PAD operates between the ground potential VsS and the power supply potential Vcc, the N-channel MISFETQ, □ is set to the signal "1" by the control circuit.
``'' is applied and becomes conductive.As a result, the pull-up MISFETQ, , is connected to the wiring 11C, and the signal applied through the terminal PAD is delayed for a predetermined time.

On the other hand, when the signal applied to the internal circuit IN through the terminal PAD is operated between the ground potential Vss and a potential higher than the power supply potential Vcc, for example, when applying the EPROM write signal Vpp12.5V, N Channel M
ISFETQ, □ is a signal “0” by the control circuit.
A level is applied and it becomes non-conductive. As a result, P
The channel MIS FET Qpx is separated from the wiring 11C to prevent the signal applied to the terminal PAD (eg, write signal Vpp12.5V) from flowing toward the power supply potential ■cc.

Next, the structure of the device constituting the circuit will be explained with reference to FIGS. 1 and 2.

In FIGS. 1 to 3, 1 is a semiconductor substrate (hereinafter referred to as the substrate) made of N-type single crystal silicon, and a P° type well region 2 is formed in the region where the N-channel MISFET is formed. ing. Reference numeral 4 denotes a field insulating film made of a silicon oxide film formed by selective thermal oxidation on the surface of the substrate 1, and a P channel stopper region 3 is formed in the lower part thereof except for the well region 2.

The P channel M I S F E T Q p 1 includes a P6 type half region 6 which is a source and drain region on the surface of the substrate 1, a gate insulating film 5 made of a silicon oxide film formed by thermal oxidation on the surface of the substrate 1, for example. It is composed of a gate electrode 8A made of a polycrystalline silicon film formed by CVD. A wiring 11A11A made of, for example, a first layer of aluminum film for supplying a power supply potential Vcc is connected to the source region 6 through a connection hole 10.

The wiring 11A is connected to the substrate 1 through a contact hole 10, and an N-type semiconductor region 13 is provided on the surface of the substrate 1 below the contact hole 10 to establish ohmic contact. Gate electrode 8A is at ground potential Vss
The wiring 11 made of the first layer of aluminum film is supplied with
connection hole 10 through the connection hole 10.

The N-channel MISFETQ is composed of an N-type semiconductor region 7 which is a source and a drain formed on the surface of the well region 2, a gate insulating film 51 made of a silicon oxide film, and a gate electrode 88 made of a polycrystalline silicon film, for example. are doing. The N-type semiconductor region 7, which is a source region, is connected to a wiring 11c made of a first layer aluminum film extending from a bonding pad PAD through a connection hole 10.

The N° type semiconductor region 7, which is a drain region, is connected to a P
It is connected to the P'' type semiconductor region 6 which is the drain region of the channel MISFETQ.

P-channel MIS forming the internal circuit IN
The FET Qpx is composed of a gate electrode 8c made of a polycrystalline silicon film, a source and drain made of a P'' type semiconductor region 6, and a gate insulating film 5 made of a silicon oxide film. It consists of a source and drain made of an N1 type semiconductor region 7 formed in the well region 2, a gate electrode 8° made of a polycrystalline silicon film, and a gate insulating film 5 made of a silicon oxide film.

A wiring lie is connected to the gate electrodes 8c and 8° through a connection hole 10. A wiring 11. made of an aluminum film that supplies a ground potential Vss to the N0 type semiconductor region 7, which is the source region of the N-channel MISFETQ. are connected through the connection hole 10. In addition, wiring 11. is connected to the surface of the well region 2 through the connection hole 10.

Wiring 11 of this well region 2. By providing a P'-type semiconductor region 12 on the surface to which the two electrodes are connected, ohmic contact is established. N-channel MIS
Drain 7 of FETQ, , and P-channel MISFETQ
A wiring 11 made of aluminum film is connected between the drains 6 of □.
g is connected through the connection hole 10. P channel M
Wire 1 to source 6 of I S F E T Q p
1A is connected through the connection hole 10.

When the signal applied to the terminal PAD is operated between the ground potential VsS and a potential 1 higher than the power supply potential Vcc, for example, the write potential Vpp (for example, 12.5 V), the potential is applied to the N-channel MISFETQ through the wiring 11f: , is applied to the source region (N” type semiconductor region) 7. At this time, the gate electrode 8. is set to “O” by the control circuit.
level, N channel M I S F E T
Make QN□ non-conductive.

Since the P<-> type well region 2 is set to the ground potential Vss, for example Ov, a reverse bias state is created between the N<-> type semiconductor region 7 and the well region 2. Therefore, a potential equal to or higher than the power supply potential Vaa applied to the interconnect 11A11e is applied to the P channel M
It does not flow to the wiring 11A through ISFETQ, , and does not flow to the well region 2.

On the other hand, when the signal applied to the terminal PAD is operated between the ground potential Vss and the power supply potential Vcc, the control circuit sets the gate electrode 88 to the "1" level and makes the N-channel MISFET Q,1 conductive. This connects the P-channel MISFE T Qpz (pull-up MISFET) to the wiring 11e.

Next, a specific usage example of the N-channel MISFETQ will be explained.

FIG. 4 is a block diagram of a microcomputer configured on one semiconductor chip 1.

In Fig. 4, CPG is a clock pulse generator, A is an accumulator, OCR is a condition code register, SP is a stack pointer, PC is a program counter, CPU is a central processing unit, ALU is an arithmetic logic unit, and EPROM is an electrical unit.
Programmable ROM, RAM is Ra
ndomAccess Memory, TIMER is a timer, A/D is an analog-digital converter, SC
I is serial communication interface, D
-REG is data direction register, A-PORT, B-P
ORT and C-PORT are A boat, B port, respectively.
This is the C port. BUS is a path.

A plurality of terminals PAD are provided around the chip 1.

Among these multiple terminals PAD, A-PORT, B-
Input terminal PAD coming out from PORT, C-PORT, etc.
Alternatively, the input/output common terminal PAD has a P-channel MIS
A pull-up MISFET consisting of an FET is provided.

In particular, the terminal PAD (RESET/VPP) is connected to the ALU, CPU, and CPG when the microcomputer is powered on.
terminals PAD and E for resetting to the initial state.
Write to PROM VP p (Used as a common terminal for 7 times. The Yr πτ signal has an amplitude between the ground potential Vss and the power supply potential Vac, whereas the write potential VP
P is an amplitude from the ground potential Vss to, for example, 12.5V. There, terminal PAD (RESET/Vpp)L
: is a pull-up MISFETQ as shown in Figure 5.
N-channel MISFET QN1 between P1 and wiring 11°
is provided, and this is the control signal "1'" di O
71. Note that FIG. 5 shows an equivalent circuit of some circuits in the microcomputer. The control signals “1” and “0” are the central processing unit C
Sent from PU. In other words, when the reset circuit is used, #1 tj is sent out and the EPROM write VP
At P, (# Otj is sent out, surrounded by a dotted line, R
The circuit shown with ESET is the reset circuit, which connects the central processing bag [CPU,
It is connected to circuits such as the arithmetic logic unit ALU and condition code register OCR. The switch SW is conductive when the terminal PAD (RESET/Vpp) is used as a reset terminal, that is, when the semiconductor chip 1 is reset, and when the terminal PAD (RESET/Vpp) is used as a write terminal, that is, it writes information in the EPROM. Sometimes there is no conduction.

As explained above, an N-channel MISFETQ, , is provided between the pull-up MISFETQ, □, which is a P-channel MISFET, and the wiring 11c extending from the terminal PAD, and is made conductive when the circuit is reset, and is turned off during writing. By making it conductive, the power supply potential V is applied to the terminal PAD where the pull-up MISFET is provided.
Signal 6 having a higher potential than cc can be applied. Due to this.

Two types of signals with different levels can be applied to one terminal.

The present invention has been specifically described above based on examples.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, it may be configured as shown in FIG.

Q, is a pull-up M consisting of an N-channel MISFET.
ISFET, Q, is an N-channel drive MISFET. G is the gate electrode of MISFETQ, □, G2 is M
This is the gate electrode of ISFETQN3. N-channel MI
SFETQ, , is made conductive when the signal applied to the terminal PAD is operated between the ground potential Vss and the voltage level Vcc, and is turned on when the signal applied to the terminal PAD is operated between the ground potential Vss and the power supply potential 70°.
When a signal operating at a potential of 0 or more is applied, it is brought into a non-conducting state.

In addition, as shown in FIG. 7, N-channel MISF E
A pull-up MISFET consisting of a P-channel MISFET QPt may be configured between TQH□ and the power supply potential Vcc terminal.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

Pull-up MISFE consisting of P-channel MISFET
The pull-up MISFET is provided by providing an N-channel MISFET between the wiring extending from the T and the terminal (bonding pad), and making it conductive during circuit reset and non-conductive during writing. A signal with a higher potential than the power supply potential Vcc can be applied to the terminal. This allows multiple types of signals with different levels to be applied to one terminal.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of the vicinity of a bonding pad of a semiconductor integrated circuit device, and FIG. 2 is a sectional view taken along the line AA in FIG. 1. 3 is an equivalent circuit of FIG. 1, FIG. 4 is a block diagram of a microcomputer, and FIG. 5 is an equivalent circuit of a part of the microcomputer. FIG. 6 shows an equivalent circuit of a modified example of the circuit, and FIG. 7 shows an equivalent circuit of another modified example. In the figure, 1... semiconductor substrate, 2... well region, 3...
... P channel stopper region, 4... Field insulating film, 5... Gate insulating film, 6... P° semiconductor region,
7...N° semiconductor region, 8... Gate electrode, 9...
・Insulating film, 10... Connection hole, 11... Wiring (aluminum film), PAD... Terminal (bond-in pad)
, CPU...Central processing unit, CPG...Clock pulse generator, A...Accumulator, OCR・
...Condition code register, SP...Stack pointer, PC...Program counter, ALU...
...Arithmetic logic unit, EPROM, PAM...
Memory, TIMER...timer, A/D...analog-digital converter, SCI...serial communication interface. D-REG...Data direction register, A-PORT,
B-POR'l C-PORT...Port, BUS・
...Bus, RESET...Reset circuit. Figure 2 Figure 3 V/CC SS Figure 4 Figure 5

Claims (1)

[Claims] 1. A first circuit to which a first potential that is positive or negative with respect to a reference potential is applied, and a second circuit to which a second potential that is more positive or negative than the first potential is applied. circuit, and applies the first potential or the second potential to the first circuit or the second circuit through the same external terminal, the semiconductor integrated circuit device comprising: the external terminal, the first circuit, and the second circuit. A control MISFET is connected to the wiring connecting the control MISFET, and when supplying a first potential to the first circuit, the control MISFET
A semiconductor integrated circuit device characterized in that the control MISFET is made non-conductive when T is made conductive and the second potential is supplied to the second circuit. 2. The semiconductor integrated circuit device according to claim 1, wherein the external terminal is a bonding pad. 3. The control MISFET is an N-channel MIS
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a FET, and a pull-up MISFET consisting of a P-channel MISFET is connected between the FET and a power supply potential wiring. 4. The first circuit is a circuit operated between a power supply potential Vcc and a circuit ground potential Vss, and the second circuit is operated at a potential higher than the power supply potential. A semiconductor integrated circuit device according to scope 1.