JPS63238642A - マイクロプロセツサ・アナライザ - Google Patents
マイクロプロセツサ・アナライザInfo
- Publication number
- JPS63238642A JPS63238642A JP62072623A JP7262387A JPS63238642A JP S63238642 A JPS63238642 A JP S63238642A JP 62072623 A JP62072623 A JP 62072623A JP 7262387 A JP7262387 A JP 7262387A JP S63238642 A JPS63238642 A JP S63238642A
- Authority
- JP
- Japan
- Prior art keywords
- data
- trigger
- address
- output
- latch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62072623A JPS63238642A (ja) | 1987-03-26 | 1987-03-26 | マイクロプロセツサ・アナライザ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62072623A JPS63238642A (ja) | 1987-03-26 | 1987-03-26 | マイクロプロセツサ・アナライザ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63238642A true JPS63238642A (ja) | 1988-10-04 |
| JPH0434183B2 JPH0434183B2 (enrdf_load_stackoverflow) | 1992-06-05 |
Family
ID=13494697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62072623A Granted JPS63238642A (ja) | 1987-03-26 | 1987-03-26 | マイクロプロセツサ・アナライザ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63238642A (enrdf_load_stackoverflow) |
-
1987
- 1987-03-26 JP JP62072623A patent/JPS63238642A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0434183B2 (enrdf_load_stackoverflow) | 1992-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0042422B1 (en) | Diagnostic circuitry in a data processor | |
| CA2002325C (en) | Method for observing the progress in time of an object program | |
| US9460814B2 (en) | Memory tester design for soft error rate (SER) failure analysis | |
| US4970679A (en) | Pulse input apparatus | |
| JPS63238642A (ja) | マイクロプロセツサ・アナライザ | |
| JP2620072B2 (ja) | 論理回路試験装置 | |
| JP2000121686A (ja) | 閾値テスト回路 | |
| JP3060650B2 (ja) | パターンメモリ装置 | |
| SU377678A1 (ru) | УСТРОЙСТВО дл АНАЛИЗА СТРУКТУРЫ СТРОИТЕЛЬНЫХ | |
| KR200238130Y1 (ko) | 마이크로 콘트롤러 | |
| JPH0716189Y2 (ja) | ブレーク回路 | |
| JPH02268520A (ja) | 逐次比較型アナログ・ディジタル変換回路 | |
| JPH0991165A (ja) | トレース型論理解析装置のトリガ方式 | |
| JPH05120079A (ja) | 動作履歴記憶装置 | |
| JPH05297067A (ja) | Lsiテスタ | |
| Afanas’ ev et al. | Control and monitoring of the trigger system of the DIRAC experiment | |
| JPS61243377A (ja) | Lsi試験装置 | |
| JPS60168236A (ja) | マイクロプログラム制御装置 | |
| JPS60222778A (ja) | ロジツクアナライザ | |
| JPH02242345A (ja) | マイクロプロセッサ・アナライザ | |
| JPH052899A (ja) | 半導体集積回路 | |
| JPS63109548A (ja) | マイクロプロセッサ・アナライザ | |
| JPH01200823A (ja) | パリティ検出装置の検査方法 | |
| JPH0635748A (ja) | デバッグ方法およびデバッグ装置 | |
| JPH01106232A (ja) | マイクロプロセッサ・アナライザ |