JPS63232688A - Rectifier circuit - Google Patents

Rectifier circuit

Info

Publication number
JPS63232688A
JPS63232688A JP6396787A JP6396787A JPS63232688A JP S63232688 A JPS63232688 A JP S63232688A JP 6396787 A JP6396787 A JP 6396787A JP 6396787 A JP6396787 A JP 6396787A JP S63232688 A JPS63232688 A JP S63232688A
Authority
JP
Japan
Prior art keywords
signals
output signals
output
amplifier
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6396787A
Other languages
Japanese (ja)
Inventor
Makoto Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP6396787A priority Critical patent/JPS63232688A/en
Publication of JPS63232688A publication Critical patent/JPS63232688A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent fluctuation of detection output signals caused by the variation of a receiving state, by extracting only AC components which are voice signals from the detection output signals and producing AGC controlling signals by adding the voice signals to the detection output signals.
CONSTITUTION: The output signal of a tuner is amplified by an IF amplifier 2 and detected and rectified by a detector 3. The DC component of the detect signal of the detector 3 is cut off by a capacitor 10 and, after the phase is inverted by an amplifier 11 having an amplification factor '1', the DC component is cut off by another capacitor 12. When detection output signals B containing DC components are connected with the output of the capacitor 12 by means of a resistance 13, voice signals are offset and only DC components remain. The DC output signals are proportional to the carrier level of inputted radio waves. Therefore, when the amplification factor of the IF amplifier 2 is finally controlled by using the DC output signals as the control signal of an AGC controlling section 9, a constant output level can be obtained at an output terminal 6.
COPYRIGHT: (C)1988,JPO&Japio
JP6396787A 1987-03-20 1987-03-20 Rectifier circuit Pending JPS63232688A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6396787A JPS63232688A (en) 1987-03-20 1987-03-20 Rectifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6396787A JPS63232688A (en) 1987-03-20 1987-03-20 Rectifier circuit

Publications (1)

Publication Number Publication Date
JPS63232688A true JPS63232688A (en) 1988-09-28

Family

ID=13244575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6396787A Pending JPS63232688A (en) 1987-03-20 1987-03-20 Rectifier circuit

Country Status (1)

Country Link
JP (1) JPS63232688A (en)

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