JPS63229539A - Memory access controller - Google Patents

Abstract

PURPOSE:To perform at a high speed such a process that must assure access sequence properties by suppressing the supply of address information to the holding means for address information in case it is decided that the address information are held by all holding means. CONSTITUTION:When an address (d)10111 is received from an address register 1, a request is sent to a buffer part 6 since two lower order bits of the address (d)10111 are equal to value 11. Then an address (e)10100 is sent from the register 1 and therefore a request is given to a buffer part 3 since two lower rank bits of the address (e)10100 is equal to value 00. In this case, the valid addresses are held by all entries of an address buffer 31 and therefore a request number counter 34 is equal to value 111. Thus a check circuit 36 sends value 1 to a control circuit 2 via a signal line 301 and the circuit 2 gives no request to the register 1 for transmission of an address. Hereafter the transmission of the address (e)10100 is held until an idle entry is secured in the buffer 31.

Description

TECHNICAL FIELD The present invention relates to a memory access control device, and more particularly to a memory access control device that controls memory access in which the order of accessed data is predetermined.

Prior Art Conventionally, in this type of memory access control device, only one data bus is provided to the memory in order to guarantee the order of access, and the data sent from the memory is transferred one by one. They are processed in order.

In such conventional memory access control devices, only one data bus is provided to the memory in order to guarantee ordering of accesses, so a certain access may be delayed due to factors such as memory bank contention. If it is, subsequent data cannot be accessed, and it is difficult to speed up processing that requires guaranteeing the order of access.

Purpose of the Invention The present invention was made in order to eliminate the above-mentioned drawbacks of the conventional ones, and an object of the present invention is to provide a memory access control device that can perform processing that requires guaranteeing the order of access at high speed. shall be.

RMO and filtering A memory access control device according to the present invention is a memory access control device that performs ordered access to a plurality of memory modules consisting of a plurality of independently operable banks, and includes A holding means for holding ordered address information, a use state determining means for determining a use state of the bank, and a holding state determining means for determining a holding state of the holding means are provided in correspondence with each of the memory modules. , when the bank accessed by the address information from the holding means is determined to be in use by the use state determining means, the address information is stored in the holding means, and the address information is stored in all of the holding means. The present invention is characterized in that supply of the address information to the holding means is suppressed when the holding state determining means judges that the address information is held.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a memory access control device according to an embodiment of the present invention includes an address register 1 that temporarily stores addresses for access, a control circuit 2, and buffer units 3 to 6 that hold addresses from the address register 1. , and memory modules 7 to 10 to which addresses are supplied from buffer units 3 to 6, respectively.

Address register 1 outputs part of the address to control circuit 2 by signal @ 101, and the remaining address is output to signal line 1.
02 to the buffer units 3 to 6, respectively.

FIG. 2 is a block diagram showing the detailed configuration of the buffer units 3 to 6 in FIG. 1. In the figure, the buffer section 3 includes an address buffer 31 to which address information is input via a signal line 102, a write address counter 32 that outputs a write address to the address buffer 31, and a read address counter 32 that outputs a read address to the address buffer 31. It is composed of an address counter 33, a request number counter 34, a bank check circuit 35, and a check circuit 36.

Address information from the address register 1 is input to the address buffer 31 by a signal 1102. The write request signal 2051 sent from the control circuit 2 is connected to the address buffer 31 as a write enable, and is also connected as a count-up signal that adds a value of "1" to the write address counter 32 and the number of requests counter 34. .

The output of the write address counter 32 is sent to the address buffer 31 as a write address via a signal line 303.

Address information read from the address buffer 31 by the read address from the read address counter 33 is sent to the memory module 7 via a signal line 302, and a part of this address information is sent to the bank check circuit 35 via a signal line 305.

The bank check circuit 35 checks the usage state of the bank to be accessed by the address read from the address buffer 31, and if it is unused, sends a request to the memory and registers the newly used bank. Has a function.

Further, the bank check circuit 35 sends a count-up signal to the read address counter 33 by adding the value "1" to the read address counter 33 via the signal line 306.
For 4, a countdown signal is sent that decrements the value "1".

The output of the read address counter 33 is sent to the address buffer 31 as a read address via a signal line 304. Furthermore, when both the write address counter 32 and the read address counter 33 are counted up by the maximum value of the address in the address buffer 31, they immediately return to "0".
will be reset to 1.

The request number counter 34 is a counter that indicates valid address information existing in the address buffer 31, and its output is sent to the check circuit 36 via a signal line 307. Quest number counter 34 from hair with check circuit 36
If the value is 0, it is determined that valid address information exists in the address buffer 31,
Signal the bank check instruction signal! ! It is sent to the bank check circuit 35 by 2308.

Furthermore, if the number of entries in the request/stack number counter 34 is equal to the number of entries in the address buffer 31, no more requests will be accepted, and therefore, an inhibition signal is sent to the control circuit 2 from the signal line 301.

Although the buffer unit 3 is configured in this way, the other buffer units 4 to 6 are also configured in the same manner as the address buffers 41, 51, .
61, write address counter 42.52.62,
It is composed of a read address counter 43.53.63, a request number counter 44.54.64, a bank check circuit 45.55.65, and a check circuit 46.56.66. The output address information is sent to the memory module 8.9.10 through the signal lines 402, 502, 602, respectively, and the inhibition signals from the check circuits 46, 56.66 are sent to the signal line 4, respectively.
01, 501.601 to the control circuit 2.

1111 Taro circuit 2 is signal @ line 301, 401.501
．． Inhibition signal input by each 601 and signal line 1
Write request signals for the buffer units 3 to 6 are generated from part of the address information input by 01, and these write request signals are sent to the buffer units 3 to 6, respectively, through signal lines 201.
~204. At the same time, an address information sending request signal to the address register 1 is sent to the signal line 2.
Send by 05.

FIG. 3 does not show the contents of address register 1 in FIG. 1;
FIG. 4 is a diagram showing the configuration of each memory module 7 to 10 in FIG. 1, and FIGS. 5 and 6 are diagrams showing the operation of an embodiment of the present invention and the addresses and access order of the layers. It is a diagram. The operation of one embodiment of the present invention will be explained using these FIGS. 1 to 6.

To simplify this explanation, as shown in FIG.
The lower 5 bits indicate the bank address. Also, the lower 5 of this address
It is assumed that the lowest two bits are sent to the control circuit 2, and the remaining three bits are sent to the buffer units 3-6.

At this time, it is assumed that the number of banks is 25=32, and the banks belonging to each boat are respectively addressed as shown in FIG. That is, since the bank belonging to memory module 7 is 0.4.8°, the lowest two bits of the address for memory module 7 are "o o", and the address for each of memory modules 8 to 10 is "o o". The lowest two bits of the address are '01', '“i
o”, “11”. Each memory module 7
10, the 10 bits excluding the least significant two bits are sent out from the buffer units 3-6.

Further, the address buffers 31, 41, 51, and 61 are each capable of holding addresses of 8 entries. Therefore, write address counters 32.42, 52.62
The read address counters 33.43 and 53.63 each consist of 3 bits.

Banks and address buffers in memory modules 7-10? 31, 41, 51, and 61 are all unused, the address register 1 is stored in the contents and order shown in FIG.
The operation when sent from is explained below. still,
The contents of the 7-bit address within the bank are indicated by ae.

The lower two bits “01” of the first address “a11001” are sent to the address register 1 by the signal line 101.
When the address transmission request signal is sent to the control circuit 2 from the signal line 401, the control circuit 2 learns from the signal line 401 that the output of the buffer section 4 is 1 Uroj, that is, the address buffer 41 is empty, and sends the address sending request signal to the address register 1 using the signal 1205. At the same time, an advance signal is sent to the buffer unit 4 via the signal line 202.

Since the advance signal from the signal line 202 is [rlJ, the write address counter 42 (direct) is incremented by 1 and becomes the value "OO1", and the write enable also becomes the value "1", so the address buffer 41 has 'a110'. is set.

Further, since the request number counter 44 is also counted up by +1 and becomes the value "001", the check circuit 46 outputs the value "1" from the signal line 408 and outputs the value "1" to the address buffer 44.
The bank check circuit 45 is notified that there is a valid request within 1.

The bank check circuit 45 checks the sixth bank, ie, the bank "25" corresponding to the bank "'110" sent through the signal line 405. Since all banks are currently unused, the bank check circuit 45
checks bank "25", determines that bank "25" is available, sends a request signal to memory module 8, and also registers that bank "25" is in use. do. Furthermore, the bank check circuit 45 outputs the value "1" through the signal line 406, adds "1" to the read address counter 43, and subtracts "1" from the value of the request number counter 44.

As a result, the request number counter 44 becomes the value "0" again, and the value "0" is sent through the signal line 408 as a bank check instruction signal.

The second address "b 11001" is the same memory module 8 and bank "25" as the first address "alloo", so the first address "ailoo"
The bank check circuit 4 operates in the same manner as in the case of
5 examines bank "25", but the first address "a"
11001", so no request is sent to the memory module 8. At this time, the address "b11" is stored in the address buffer 41.
0” is set and registered.

Also, since the output of the bank check circuit 45 is "0" through the signal line 406, the read address counter 43
And the value of the request number counter 44 does not change.

When the value "io" of the lower two bits of the third address "collo" is sent from the address register 1 to the control circuit 2 via the signal line 101, the control circuit 2 receives the output of the buffer section 5 via the signal line 501. Knowing that the value is "O", that is, the address buffer 51 is empty,
An address sending request signal is sent to the address register 1 through the signal line 205, and an advance signal is sent to the buffer section 5 through the signal line 203.

Hereafter, in the same way as the operation for the first address "'ai1ooi", the address buffer? 51 “CO11”
is set, and a request signal is sent to the memory module 9. It also registers that bank "14" corresponding to bank "011" is in use.

As can be seen from the above explanation, each memory module 7~
10, address buffer 31°41.51.
61, even if a bank belonging to a certain memory module 7 to 10 is in use, other memory modules 7
If the request is for ~10, this request can be issued. In addition, each address buffer 31
．． 41゜51.61 each have multiple entries, so
Each buffer section 3 to 6 can hold a plurality of addresses. The request number counters 34, 44, 54, 64 of each buffer section 3 to 6 correspond to the address buffers 31 and 41.
．． 51. Unless it shows a number of entries of 61, i.e. the address buffer? If there is space in 31.41.51.61, address data can be sent from address register 1.

Next, regarding the operation when a certain address buffer F31.41.51.61 holds requests for the number of entries, for example, when the address buffer 31 holds addresses for 8 entries, FIG. The following describes the operation when access is made in the contents and order shown in .

When address ``d10111'' is sent from address register 1, the lower 2 of address ``d10111''
Since the bit has a value of "11", a request to the buffer section 6 is sent.

However, the address "e" is then read from address register 1.
10100” is sent, the address “e” is sent.
The lower two bits of ``10100'' are the value ``o o'', so this is a request to the buffer section 3.
At this time, since valid addresses are held in all entries in the address buffer 31, the request number counter 34 is "i i 1".

Therefore, the check circuit 36 is directly connected to the signal line 301.
1" is sent to the control circuit 2, and the control circuit 2 does not request the address register 1 to send an address.

After that, address buffer? The sending of address ``e10100'' is delayed until entry 31 becomes vacant.

In this way, the address buffers 31.41.51.6 are provided corresponding to each of the memory modules 7 to 10 and hold ordered address information for access.
When it is determined that the bank accessed by the address information from 1 is in use, the address information is stored in the address buffer 31.41.51.61, and all addresses in this address buffer 31.41.51.61 By suppressing the supply of address information to the address buffer 31.41.51.61 when it is determined that the information is held, the access class maintains the order of access to ordered addresses. , and request processing can be performed in parallel. Also, even if requests concentrate on a certain bank, the address of the requests for that bank can be stored in the address buffer 31.41.51.
Since it can be held at ゜61, it is possible to reduce the proportion of waiting requests for other connected banks, and it is possible to execute processing that requires guaranteeing the order of access at high speed. .

As explained above, according to the present invention, a bank is provided corresponding to each memory module and accessed by address information from a holding means that holds ordered address information for access. When it is determined that the address information is in use, the address information is stored in the holding means, and when it is determined that the address information is held in all the holding means, the supply of address information to this holding means is suppressed. This has the effect that processing that requires guaranteed access order can be executed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the detailed configuration of the buffer section in FIG. 1, and FIG. 3 is a block diagram showing the contents of the address register in FIG. 1. 4 is a diagram showing the configuration of each memory module in FIG. 1, and FIGS. 5 and 6 are diagrams showing addresses and access order for explaining the operation of an embodiment of the present invention. be. Explanation of symbols of main parts 1...Address register 2...Control circuits 3-6...Buffer unit 7-]0...Memory module 31.41゜51.61...Address buffer 35.45゜55.65...Bank check circuit 36.46
゜

Claims (1)

[Claims] A memory access control device that performs ordered access to a plurality of memory modules consisting of a plurality of independently operable banks, the memory access control device comprising: a holding means for holding ordered address information for said access; A use state determining means for determining a use state of a bank and a holding state determining means for determining a holding state of the holding means are provided corresponding to each of the memory modules, and the memory module is accessed by the address information from the holding means. The address information is stored in the holding means when the bank is determined to be in use by the use state determining means, and the holding state determining means determines that the address information is held in all of the holding means. 1. A memory access control device, wherein supply of the address information to the holding means is suppressed when the address information is stored.