JPS63228084A - Reliability evaluating method for semiconductor device - Google Patents
Reliability evaluating method for semiconductor deviceInfo
- Publication number
- JPS63228084A JPS63228084A JP6152487A JP6152487A JPS63228084A JP S63228084 A JPS63228084 A JP S63228084A JP 6152487 A JP6152487 A JP 6152487A JP 6152487 A JP6152487 A JP 6152487A JP S63228084 A JPS63228084 A JP S63228084A
- Authority
- JP
- Japan
- Prior art keywords
- deterioration
- voltage
- drain
- electrode
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 14
- 239000004065 semiconductor Substances 0.000 title claims 3
- 230000006866 deterioration Effects 0.000 claims abstract description 36
- 238000010408 sweeping Methods 0.000 claims abstract description 5
- 230000032683 aging Effects 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 4
- 238000012360 testing method Methods 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 5
- 230000001133 acceleration Effects 0.000 abstract description 2
- 230000035882 stress Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 238000011156 evaluation Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ＭＯ８型電界効果トランジスタの実動作によ
り近い状態での経時劣化を加速評価するための新規な信
頼性評価方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a novel reliability evaluation method for accelerated evaluation of aging deterioration of an MO8 field effect transistor in a state closer to actual operation.
従来の技術
ＭＯ８型電界効果トランジスタ（ＭＯＳＦＥＴ）は、素
子の微細化により高密度・高集積化される反面、信頼性
上の様々な問題を生ずる。中でも動作時におけるドレイ
ン近傍の高電界領域で加速さし高エネルギーを得たホッ
トキャリアにより引き起こされるホットキャリア劣化は
、素子の微細化を進める上で非常に重要な問題となって
いる。Conventional MO8 type field effect transistors (MOSFETs) have become highly dense and highly integrated due to miniaturization of elements, but on the other hand, various reliability problems arise. Among these, hot carrier deterioration caused by hot carriers that are accelerated and have high energy in the high electric field region near the drain during operation has become a very important problem in advancing the miniaturization of devices.
従来このホットキャリアの評価には、ドレイン電圧一定
のもとてゲートに基板電流が最大となるようなドレイン
電圧の約半分の電圧（例えばドレイン電圧を７ｖとしだ
時ゲート電圧は３．５Ｖ）を印加して評価を行っていた
。この方法による試験回路を第６図に示す。ストレスは
、試験に供せられたｎ−ｃｈＭＯ８ＦＫＴのゲート６と
ドレイン４にそれぞれ前述の所定のＤＣ電圧を印加して
行う。Conventionally, to evaluate hot carriers, a voltage that is about half the drain voltage (for example, when the drain voltage is 7 V, the gate voltage is 3.5 V) is used to maximize the substrate current to the gate with the drain voltage constant. was applied and evaluated. A test circuit using this method is shown in FIG. Stress is performed by applying the aforementioned predetermined DC voltage to the gate 6 and drain 4 of the n-ch MO8FKT subjected to the test, respectively.
劣化の評価はこのようなストレス印加とその前後に行う
デバイスの特性の測定とを繰り返すことにより特性の経
時劣化を評価する。Deterioration is evaluated by repeating such application of stress and measurement of device characteristics before and after the application of stress.
しかし実際の集積回路ではこのようなゲート電圧がドレ
イン電圧の約半分の状態は、過渡時において一瞬存在す
るだけで実動作時の劣化とは同一とは言えない。実際に
第６図に示したようなＣＭＯＳインバータ回路のゲート
８に立ち上がりの異なるパルスを印加してｎ−ｃｈＭＯ
ＳＦＥＴ １の劣化を評価したところ、基板電流の総発
生量が同一になる点でＤＣストレスと比較すると第７図
に示すようにＤＣストレスに比ベパルスを印加した方が
劣化が大きくなる。またこの差はパルスの立ち上がりが
急峻なほど顕著となる。However, in an actual integrated circuit, such a state in which the gate voltage is approximately half the drain voltage exists only momentarily during a transient period, and cannot be said to be the same as deterioration during actual operation. Actually, by applying pulses with different rises to the gate 8 of the CMOS inverter circuit as shown in FIG.
When the deterioration of SFET 1 was evaluated, the deterioration was greater when compared to DC stress in that the total amount of substrate current generated was the same, as shown in FIG. 7, when a comparative pulse was applied to DC stress. Moreover, this difference becomes more pronounced as the rise of the pulse becomes steeper.
発明が解決しようとする問題点
以上述べたように従来のホットキャリア劣化評価法では
ドレイン電圧一定のもとて劣化が最も顕著であるような
ゲート電圧を印加することにより経時劣化の評ｇｆｆＪ
を行うため実動作での劣化と異なるという問題があった
。Problems to be Solved by the Invention As described above, in the conventional hot carrier deterioration evaluation method, evaluation of aging deterioration is performed by applying a gate voltage at which the deterioration is most significant while keeping the drain voltage constant.
There was a problem that the deterioration was different from that in actual operation.
問題点を解決するための手段
本発明は、上記問題点全解決するためドレインに一定の
電圧を印加した状態で、ゲートに印加する電圧をスウィ
ーブさせながらホットキャリア劣化の評価を行う。Means for Solving the Problems In order to solve all of the above problems, the present invention evaluates hot carrier deterioration while sweeping the voltage applied to the gate while applying a constant voltage to the drain.
作用
本発明は、上記した方法により実動作に近い状態でＭＯ
Ｓ型電界効果トランジスタのホットキャリア劣化の加速
評価を行うことができる。Effect of the present invention is to perform MO in a state close to actual operation by the method described above.
Accelerated evaluation of hot carrier deterioration of S-type field effect transistors can be performed.
実施例
本発明の特許請求の範囲にもとづく具体的な実施例を図
面を用いて説明する。第１図は本発明の方法により、ｎ
−ｃｈＭＯＳＦＩｃＴのホットキャリア評価を行うだめ
の回路図を示す。試験に供せられるｎ−ｃｈＭＯＳＦＥ
Ｔ １のソース電極２及び基板電極３はグランドに接続
し、ドレイン電極４には外部電源６により例えば７ｖの
ドレイン電圧（ＶＤ）を印加する。ゲート電極６にはパ
ルスジェネレータ７により第２図ａ及びｂに示したよう
な例えばスウィープ（掃印）幅がＯ〜７ｖの鋸波あるい
は三角波状のパルスを印加する。本実施例では、ｎ−ｃ
ｈＭＯＳＦＥＴとしてチャンネル長ＬＯμｍ１チャンネ
ル幅２０μｍ１ゲート電極はポリＳｉ、表面保護膜とし
てプラズマ窒化膜を用いたトランジスタを使用した。Embodiments Specific embodiments based on the claims of the present invention will be described with reference to the drawings. FIG. 1 shows that by the method of the present invention, n
- A circuit diagram for hot carrier evaluation of chMOSFIcT is shown. n-chMOSFE used for testing
The source electrode 2 and substrate electrode 3 of T 1 are connected to the ground, and a drain voltage (VD) of, for example, 7 V is applied to the drain electrode 4 from an external power source 6 . A pulse generator 7 applies to the gate electrode 6 a sawtooth or triangular wave pulse having a sweep width of 0 to 7V as shown in FIGS. 2a and 2b, for example. In this example, n-c
As an hMOSFET, a transistor was used in which a channel length was LO μm, a channel width was 20 μm, a gate electrode was made of poly-Si, and a plasma nitride film was used as a surface protection film.
この方法により評価したデバイスの劣化前後のサブスレ
ッシュホールド特性を第３図乙に示す。The subthreshold characteristics of the device evaluated by this method before and after deterioration are shown in Figure 3B.
同図すはドレインにＴＶ、ゲートに３．６ｖを印加した
ときの結果、同図ＣはＣＭＯＳインバータ回路を構成し
立ち上がり５ｏｎｓのパルスストレスを印加したときの
結果である。いずれの結果も基板電流総発生量が同じ点
での劣化を示している。The figure shows the result when TV is applied to the drain and 3.6V to the gate, and the figure C shows the result when a CMOS inverter circuit is configured and a pulse stress of 5 ounces is applied. Both results show deterioration at the point where the total amount of substrate current generation is the same.
本発明の方法による劣化とＣのパルスストレスの劣化ト
は共にサブスレッシュホールドスウィングＳの劣化がみ
られよく似た劣化を示していることがわかる。従って本
発明の方法が実動作と非常に近い劣化モードで劣化が引
き起こっていると考えられる。It can be seen that the deterioration caused by the method of the present invention and the deterioration caused by the pulse stress of C both show deterioration in the subthreshold swing S, and are very similar. Therefore, it is considered that the method of the present invention causes deterioration in a deterioration mode that is very similar to the actual operation.
また第４図は本方法による劣化と従来例に示したＤＣス
トレス試験による閾匝亀圧変動の経時変化を示したもの
である。同じ時間で比較したとき本方法のゲート電圧を
スウィープした方がＤＣストレスに比べ１桁程度劣化が
加速されていることが分かる。Further, FIG. 4 shows the deterioration caused by this method and the change over time in the threshold pressure fluctuation caused by the DC stress test shown in the conventional example. When compared at the same time, it can be seen that sweeping the gate voltage in this method accelerates the deterioration by about one order of magnitude compared to DC stress.
発明の効果
以上述べたように、本発明の方法によれば、従来性われ
ていたＤＣストレスによるホントキャリア劣化に比ベゲ
ートを圧をスウィーブして試験することにより次のよう
な効果が得られる。Effects of the Invention As described above, according to the method of the present invention, the following effects can be obtained by testing the real carrier deterioration due to DC stress, which has been conventionally known, by sweeping the pressure.
■ 実動作と非常に近い劣化モードでの経時劣化評価が
可能となる。■ It is possible to evaluate deterioration over time in a deterioration mode that is very similar to actual operation.
■ ＤＣＣストンスに比べ同じドレイン電圧のもとでは
劣化の加速性が１桁程度大きくなる。■ Compared to DCC STONES, the acceleration of deterioration is about one order of magnitude greater under the same drain voltage.
第１図は本発明の一実施例方法に用いるホットキャリア
評価装置の構成図、第２図は本実施例方法において被測
定ＭＯＳＦＥＴ のゲートに印加するスウィープ電圧
波形を示す波形図、第３図は評価したＦＥでの劣化前後
のサブスレッシュホールド特性を示す特性図、第４図は
本実施例方法による劣化状況を従来方法による劣化状況
と比較して示す特性図、第６図は従来のホットキャリア
評価装置の構成図、第６図はＣＭＯＳインバータ回路に
パルス’＆印加してホットキャリア評価を行うための回
路図、第７図は第６図の回路に立ち上がりの異なるパル
スを印加したときの基板電流総発生量と劣化量の関係を
示す特性図である。−１１・・・・・・試験に供せられ
たｎ−ｃｈＭＯＳＦＥＴ。
６・・・・・・外部電源、７・・・・・・パルスジェネ
レータ。
ｌ −試験に供亡ら七た
ｎ−ｃｈＭＯ５ＦＥ丁
６−外部１ ；＊。
７− パルスジエネし・−り
第１図
Ｖ。
第２図
１（α）
ｅｃｖＪ
（ｂ）
Ｖ＆（ＶＪ
第３図
ゲー ト 電 ）ｊミ （Ｖ）
第４図
ｌ０ｚｆＯ３ＩＯ４
ストレス時間 （秒う
ｌ ・−試裁に供でら枳た
ｎ−ＣｈＭＯ５ＦＥＴ
６−外＠ ＤＣＩ源
第 ５ 図
第７図FIG. 1 is a block diagram of a hot carrier evaluation device used in the method of one embodiment of the present invention, FIG. 2 is a waveform diagram showing the sweep voltage waveform applied to the gate of the MOSFET to be measured in the method of this embodiment, and FIG. A characteristic diagram showing the subthreshold characteristics before and after deterioration in the evaluated FE. Fig. 4 is a characteristic diagram showing the deterioration situation by the method of this embodiment compared with the deterioration situation by the conventional method. Fig. 6 is a characteristic diagram showing the deterioration situation by the conventional method. The configuration diagram of the evaluation device, Figure 6 is a circuit diagram for performing hot carrier evaluation by applying pulse '& to a CMOS inverter circuit, and Figure 7 is a circuit diagram of the circuit when pulses with different rising edges are applied to the circuit in Figure 6. FIG. 3 is a characteristic diagram showing the relationship between the total amount of current generation and the amount of deterioration. -11... n-ch MOSFET used in the test. 6... External power supply, 7... Pulse generator. l - Tested n-ch MO5FE Ding 6-External 1 ;*. 7- Pulse Generating Figure 1 V. Fig. 2 1 (α) ecvJ (b) V & (VJ Fig. 3 Gate voltage) j Mi (V) Fig. 4 l0zfO3IO4 Stress time (seconds ul ・- n-ChMO5FET assembled for trial use 6 -Outside @ DCI source Figure 5 Figure 7
Claims (1)
経時劣化の評価をするに際し、ドレイン電極に一定の電
圧を印加した状態で、ゲート電極に印加する電圧を掃印
することにより半導体装置の経時劣化を評価するように
してなる半導体装置の信頼性評価方法。When evaluating the aging deterioration of characteristics during operation of a MOS field effect transistor, evaluate the aging deterioration of a semiconductor device by sweeping the voltage applied to the gate electrode while applying a constant voltage to the drain electrode. A method for evaluating the reliability of a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6152487A JP2617928B2 (en) | 1987-03-17 | 1987-03-17 | Semiconductor device reliability evaluation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6152487A JP2617928B2 (en) | 1987-03-17 | 1987-03-17 | Semiconductor device reliability evaluation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63228084A true JPS63228084A (en) | 1988-09-22 |
| JP2617928B2 JP2617928B2 (en) | 1997-06-11 |
Family
ID=13173572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6152487A Expired - Fee Related JP2617928B2 (en) | 1987-03-17 | 1987-03-17 | Semiconductor device reliability evaluation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2617928B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877419A (en) * | 1996-03-14 | 1999-03-02 | Siemens Aktiengesellschaft | Method for estimating the service life of a power semiconductor component |
| US6628134B1 (en) | 1999-06-30 | 2003-09-30 | Hyundai Electronics Industries Co., Ltd. | DC stress supply circuit |
-
1987
- 1987-03-17 JP JP6152487A patent/JP2617928B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877419A (en) * | 1996-03-14 | 1999-03-02 | Siemens Aktiengesellschaft | Method for estimating the service life of a power semiconductor component |
| US6628134B1 (en) | 1999-06-30 | 2003-09-30 | Hyundai Electronics Industries Co., Ltd. | DC stress supply circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2617928B2 (en) | 1997-06-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |