JPS6321696A - Matrix display panel unit - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a light-emitting display panel device such as a gas discharge display panel (FDP), an electroluminescent display panel (KL), etc. arranged in a matrix.

Conventional display panel devices using matrix display panels include those using plasma, liquid crystal, electroluminescence (hereinafter referred to as EL), or the like as a display material.

The panel structure of such a display panel device is formed by providing matrix electrodes arranged perpendicularly to each other with a display body sandwiched between them on a glass substrate, and emitting or non-emitting light is controlled by controlling the intersection voltage of the matrix electrodes. Alternatively, display is performed by transmitting and blocking light. Now, a thin film EL display device will be specifically explained as an example of a flat display panel. FIG. 7 shows a conventional example of a thin film EL display device. The thin film KL display device is composed of an EL display panel 1, a data side drive circuit 3 that applies voltage to matrix electrodes, and a scan side drive circuit 4. The operating method of this KL display panel device will be explained. Each drive circuit consists of a shift register circuit, a launch circuit, and a high voltage driver circuit (
(not shown), and here, the driver circuit of the data side drive circuit 3 is a push-pull driver.

The driver circuit of the scanning side drive circuit 4 is a pull-only driver. The number of channels of each driver is m on the data side and n on the scanning side, corresponding to the EL display panel electrodes. The driving is performed by line sequential driving as shown in the time chart of FIG. 8. The scanning side electrodes are selected line by line and a write voltage (Vw) is applied. Meanwhile, in synchronization with this, the push-pull driver of the data side drive circuit 3 is turned on and off in response to the data signal to the data electrode, thereby applying a modulation voltage (+VM) to the selected line and zero voltage to the non-selected line. As a result, the voltage across the display cell CEL is 1v.
The state is set to M+vw1 or lVwi. Write voltage (V
By selecting w) as the light emission starting voltage of the KL display element, it is possible to cause light to emit or not to emit light depending on the presence or absence of a modulation voltage (10 VM). Line sequential scanning is performed in this way, and in order to refresh the KL display panel 1 after scanning, a refresh voltage (+'l'R) of opposite polarity is applied from the scanning electrode side.
is applied to all display elements at once to cause them to emit light again, thereby completing one frame. This driving method is generally called a simultaneous inversion field refresh driving method. By the way, when displaying data on such a matrix display device, there are two modes: a negative display mode in which the data is expressed in the form of luminescence (the background does not emit light), and a positive display mode in which the data is expressed in the form of non-emission (the background is luminous). However, an example of the image display mode is shown in Figure 9.

Show BK. For example, when the English letters H and T are displayed in the upper left edge area, H is in contact with the left edge and T is in contact with the upper edge. Although the light-emitting area 1L and the non-light-emitting area 1B have an inverted relationship between the negative display mode person and the positive display mode B, there is basically no matrix electrode in the outer peripheral area 5 of the EL display panel 1. Since it is a region, it is always in a dark state with no light emitting. Considering the characters displayed adjacent to the outer periphery 5, the outer periphery 6 and the non-light emitting area 1B do not emit light, so they can be regarded as the same area in terms of brightness. Therefore, there is no problem in the positive display mode of the person who displays the characters by emitting light, but in the negative display mode of B, which displays the characters by non-emitting light, the H
Since the left vertical line part of T and the horizontal line part of T are in contact with the outer peripheral part 4, the boundary between them is unclear.

Problems to be Solved by the Invention As described above, when the conventional matrix display panel device displays data in the positive display mode, apparent text loss occurs in the upper, lower, left, and right end areas due to adjacency with the outer periphery, which causes serious problems. The problem was that the display quality was difficult to see. On the other hand, in order to avoid this, if the characters on the outermost periphery are displayed well inside the effective display area, the display capacity will be reduced, and a new problem arises in that the effective display efficiency of the matrix display device will be greatly reduced. It will happen.

In view of this, it is an object of the present invention to provide a matrix display panel device that eliminates apparent character loss even in negative display mode without sacrificing display capacity.

Means for Solving the Problems The present invention provides X-Y machines arranged in directions that intersect with each other.
A display panel device in which a light-emitting display medium is interposed between Jnox electrodes, in which a data display area is constituted by data electrodes provided at both end areas of a data-side drive circuit and a scanning-side drive circuit, and The matrix display panel device interpolates a data control signal for controlling drive output and causes the data display area to emit light in a positive display mode.

Operation The present invention has a data display area in the shape of a letter enclosing an effective data display area with a zigzag rim, and is suitable for interpolation of a data control signal to control the drive output to the data electrodes. The data electrodes on the scanning side are scanned line by line, and a modulation voltage is applied to the data electrodes on the data side from the data side drive circuit according to the interpolated data signal during the positive display mode, so that the entire data display area is covered. By displaying the negative display data, the brightness is made the same as the background brightness of the valid data display area, and the visibility of the negative display data at the peripheral edge of the data display area is ensured.

Embodiment FIG. 1 is a circuit diagram of an EL display panel device according to an embodiment of the present invention. Here, the number of display pixels is 6 vertically.
40. The case where the horizontal value is 400 will be explained as an example. KL
Regarding the matrix electrodes of the display panel 1, on the data side, the four electrodes at both ends of the electrode group are data side border electrodes 61 and 8b, and the inner side is composed of normal data side electrodes 7D, and the same goes for the - scanning side. Four electrodes at each end of the electrode group are scan-side data electrodes 8c and 6d, and the inner side is constituted by a normal scan-side electrode 7S. As a result, the display area is the data side electrode 7D (5th to 644th lines).
and the effective data display area 7 where data is displayed by the scanning side electrodes 73 (5th to 404th lines) and the data side data electrodes 6a (1st to 4th lines), eb (645th to 648th lines).
line) and scanning side data electrode SC (1st to 4th line)
.

It is composed of a data display area 2 displayed in sd (405th to 408th lines). The data electrode 6 is connected to the output end of each drive circuit 3, 4, like the data side electrode 7D and the scanning side electrode 7S. As mentioned above, each drive circuit 3, 4 has built-in logic control circuits such as a shift register circuit, a launch circuit, and a gate control circuit, but the logic control signals to these circuits usually correspond to the number of display data. Only the signal sent from the host side is sent from the host side. In this example, the logic control signals are the clock signal CLK and data signal D for the shift register circuit, and the launch signal L for the launch circuit.
The gate control circuit requires a strobe signal STB and a clear signal OL. Only 640 data signals are sent to the data side, and 400 data signals are sent to the scanning side. Basically, the data electrodes 6 are controlled by the logic control circuit of each drive circuit 3.4, so a logic control signal for driving the data electrodes 6 is generated by the data signal generation circuit 8, and each The signal is interpolated as a logic control signal to the logic control circuit of each drive circuit 3, 4 via the OR circuit. - The data signal generation circuit 8 uses the clock signal CLK, data signal, and strobe signal ST.
B, the signal is controlled for the clear signal OL. still,
Among the output signals of the data signal generation circuit 8, the data side data signal DD' and the data side strobe signal D-3TB' are connected to the data display mode detection circuit 9, and are connected to an OR circuit only when the data display mode is the active display mode. It sends output to.

FIG. 2 is a timing chart of main logic control signals obtained by interpolating data control signals. Here, the data signal and clock signal CLK, which are essential when displaying data, are shown. One horizontal period 1H of the horizontal periodic signal HD corresponds to one scanning period of line sequential scanning. First, the data side logic control signal will be explained. Normal clock signal D-
The CLK and data signals D-D are sent for 640 data (64° CLK, 640D), but the data side drive circuit 3 has 640 data electrodes 7D (5th to 64th).
4 lines) and 4 border electrodes 6a (1st to 4th lines).
line), eb (645th to 648th line) are connected, so in order to correspond to these border electrodes 6a and 6b, 4 clocks before and after the original clock signal D-CLK and data signal D-D are used as signals corresponding to the border electrodes 6a and 6b. clock signal D-CL
K' and the data signal D- for a time corresponding to 4 clocks.
D' is generated by the Baume signal generation circuit 8 and interpolated by the OR circuit, resulting in a new clock signal of 648 data, CLK"
and data signal DD# are supplied. Taking the clock signal CLK' as an example, the first half of the interpolated clock signal, CI, is 1 to 4, the clock signal for the original 640 clocks is 5 to 644, and the second half is interpolated. The clock signal CLK' is located at 645-648. The data transfer direction on the data side on display panel 1 is the third
As shown in the figure, the data is sent from right to left, so in the area of the scanning side electrode S (5th to 404th lines), the data side border electrode sb (648th to 645th lines) is fed with the first half interpolation clock. The interpolated data signal D-D' (1-4) based on the signal CLK' (1-4 lines) is sent, and the original clock signal D-CLKC5-- is sent to the data side electrode 7D (644th line to 5th line). data signal D・D(5
~644) is sent to the data side border electrode 62L (fourth
~1st line) is the second half interpolated clock signal D-CLK.
' (645-648) interpolated data signal D-D' (
645-648) are sent.

As a result, the Baume display area 2a of the data-side border electrodes ea and sb can be completely illuminated by the interpolation signal. Regarding the scanning side logic control signals, the control signals that need to be controlled are those corresponding to the scanning side border electrodes 6c and 6d. In other words, this corresponds to the beginning and end of line sequential scanning. As with the data-side logic control signal, the clock signal and data signal will be mainly explained. The normal clock signal S, CLK is for 400 scanning electrodes (400C
LK) is sent, but if it is driven in this state, valid data will also be displayed in the Baume display area 2b by the border electrodes ec and 6d, and the original Baume function will be lost. Therefore, in order to correspond to the border electrodes 6C and 6d, a clock signal 5-CLK' for 4 clocks before and after the original clock signal S and CLK is generated by the Baume signal generation circuit 8, and is interpolated by an OR circuit to generate a new 4 clock signal.
A clock signal 5-CLK' for 08 scanning electrodes is supplied. Similarly, data signals S' and D are clock signals S and CL.
The new data signals S, D' need to be time corrected so that they are captured at the first clock of K'. As shown in FIG. 3, the scanning side data transfer direction is shifted from top to bottom one clock at a time, so the clock signal S-C:LK'
The border electrode 6c (1st to 4th lines) is scanned with the interpolated clock signals S and CLK' (1 to 4) in the first half of , and the scanning side electrode 73 ( 5th to 404th lines) are scanned, and the border electrode 6d (405th to 408th lines) is scanned by the latter half interpolated clock signal 5-CLK' (405 to 408).

Furthermore, at the scanning timing of the border electrodes 6C and 6d, the interpolation strobe signal D・STB' (
(not shown) via the data display mode detection circuit 9.
I'll supply it to the circuit. By doing so, the entire Baume display area 2b formed by the scanning side border electrodes 6C and 6d can be made to emit light. Interpolation strobe signal D-3T
Control can be similarly achieved by interpolating the clock signal D-CLK' and data signals D and D' described above without using B'.

Using the interpolation signal as described above, the entire Baume display area 2 can be caused to emit light. Incidentally, logic control signals other than those mentioned above also require interpolation in accordance with the timing of the interpolation clock signal, etc., and all of these are generated by the Baume signal generation circuit 8. Regarding valid display data, the data display mode detection circuit 9 also uses an OR circuit as an interpolation signal for the data side data signal DD' and the data side strobe signal D-STB' from the border signal generation circuit 8 only in the active display mode. However, it is turned off when in negative display mode.

Therefore, in the negative display mode, the data display area is in a non-emission state. Examples of display modes for displaying the English letters H and T in the upper left corner area are shown in FIGS. 4A and 4B. Person is in negative display mode, and B is in positive display mode. As is known, the data display area 2 is an area surrounded by the outer periphery 6 of the KL display panel 1 and the valid data display area A.

In the negative display mode, the data display area 2 is basically in a non-emissive state, so that it does not affect the characters displayed by emitting light (the display state is similar to that of conventional display devices). On the other hand, in the positive display mode, the data display area 2 is not fully illuminated, and even if non-luminous display characters are displayed in an area that is in contact with the data display area 2, the boundaries are clearly visible. It is possible to realize a display that is highly accurate and easy to see (as compared to the conventional display), and also allows display without missing characters on the screen.

FIG. 5 is a timing chart showing another embodiment of the interpolation signal as a logic control signal, and FIG. 6 is an explanatory diagram showing how the data display area 2 is driven by this control signal. be. In this embodiment, among the interpolation signals, the data side clock signal SCL' and the data signal DD' are used as a normal control signal CLK.

Interpolating only the latter half of D-D, the scanning side clock signal 5-
Similar control is performed by interpolating CLK' into only the first half of the normal control signal S and CLK. This control operation will be explained with reference to FIGS. 6A and 6B. Data side clock signal D-C
LK' has 644 clocks, and the original data signal DD is transferred from 1 to .theta.40 clocks, and the interpolated data signal DD' which becomes light emission command data is sent from 641 to 644 clocks.

In the first scanning line, the data side electrode 7D (644th to 5th
The valid data signal D-D (1 to 64o) is displayed on the border electrode 6a (5th to 1st line), and the interpolated data signal D-D' (641 to 644) is displayed on the border electrode 6b. There is no data in . In the next second scanning line, the data side clock signal D- for 644 clocks is added.
Since CLK' is transferred, the data side electrode 7D and the border electrode 6a display the same display as in the first scanning line, but the border electrode 6b (648th to 646th line) is the border electrode one scanning line before. Since the data signal supplied to 6a remains in the shift register circuit, it is apparently used as a new interpolated data signal, so that from the second scanning line onwards, the data signal is supplied to both border electrodes 6a and 6b. Ru. The data display area (■) formed by the border electrode 6b is the data display area (■) formed by the border electrode 6a.
It is controlled by the interpolated data signal before one scan of the input signal. The data signal 1 to the border electrode 6a in the first scanning line becomes the data signal υ to the border electrode 6b in the second scanning line, and the data signal 2 to the border electrode 6a in the second scanning line becomes the data signal υ to the border electrode 6a in the third scanning line. The data signal of the border i6b is repeated less than υ. As the data signal n' of the border electrode 6b of the first scanning line, the data signal of the border electrode 6a of the n-th scanning line one field before is used. Due to this operation, the clock signal D
A similar effect can be obtained by interpolating -CLK' and data signals, D' only in the latter half of the normal signal. Furthermore, regarding the scanning side logic control signal, the interpolation clock signal 5-CLK' is interpolated for four clocks only in the first half of the scanning start portion. As shown in FIG. 6B, the clock signal 5-
CLK' has 404 clocks, so the data display area (2) of the border electrode 6C (1st to 4th lines) is scanned in 1st to 4th clocks, and the scanning side chamber 17s (1st to 4th line) is scanned in 5th to 404th clocks.
5th to 404th lines) are scanned to complete one field. Next, the second field is scanned again from the first line, but at this time, in the shift register circuit of the scanning side drive circuit 4, the data transfer signal from one field before is on the 405th line, so the border error is generated in the second field. In the cases 6C and 6d, simultaneous line sequential scanning of two lines is performed. Therefore, from the second field onward, the data display areas (2) and (2) are displayed in simultaneous line sequential scanning. In this way, the same effect can be obtained for the scanning side logic control signal by interpolating the clock signal 5-CLK' only in the first half of the normal signal.

Naturally, the other control signals also need to be made into interpolated signals whose timing is matched with the clock signal by the border signal generation circuit. According to this method, the border control signal can be simplified, so the border signal generation circuit 8
It also makes configuration easier. By the way, considering the driver C used in drive circuits 3 and 4, the driver IC is mounted with a comb-shaped electrode configuration, dividing the electrodes into odd and even lines, with the data side at the top and bottom, and the scanning side at the left and right. In this case, the number of output channels and the number of installed drivers in the 640x400 pixel display of the embodiment are 32.64.
A table for the case of 68 channels is shown below.

(Leaving space below) For 32 channel and 64 channel driver ICs, there are no extra channels on the data side because the number matches the number of valid display data, so in order to provide a border display area, one data side driver IC must be placed on each of the upper and lower sides. However, with a 68-channel driver IC, there are extra channels on the data side and scanning side, so if you use this, you can achieve this by simply adding a border signal generation circuit without increasing the number of driver ICs. can. In this way, although it depends on the number of pixels to be displayed, if the driver IC has an extra number of channels, it can be configured without increasing the cost of the driver IC. In the above, the case where the present invention is applied to an EL display panel device has been described as an embodiment. However, in principle, it can also be applied to other devices such as a plasma display panel device (FDP), a fluorescent display panel device (VFD), an I, ED, etc. Any light-emitting matrix display panel device, such as a display panel device, is applicable.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a display panel having a border display area formed by border electrodes around an effective data display area is constructed, and a border signal generation circuit is used to drive the border electrodes. By interpolating control signals, line-sequential scanning similar to the conventional method is performed, and the border display area is illuminated entirely in the positive display mode, thereby preventing the apparent blurring of characters in data display at the periphery of the valid data display area. It is possible to display images with improved visibility and improved display quality.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a matrix display panel device according to an embodiment of the present invention, FIG. 2 is a timing chart of a first logic control signal for driving the border display area of the same embodiment, and FIG. 2 is a diagram showing the driving of the border display area according to the timing chart diagram; FIG. 4 is a diagram showing data display for each display mode in the same embodiment;
FIG. 5 is a timing chart of the second logic control signal for driving the border display area of the same embodiment;
The figure is a diagram showing the driving of the data display area according to the timing chart diagram of FIG. 5, and the person is on the data side. B is a diagram showing the scanning side, FIG. 7 is a circuit diagram of a conventional matrix display panel device, FIG. 8 is a drive voltage waveform diagram in the conventional example, and FIG. 9 is a diagram showing data display in each display mode in the conventional example. It is a diagram. 1... KL display panel, 2... data display area, 3... data side drive circuit, 4...
・Scanning side drive circuit, 5... outer peripheral part, e...
Border electrode, 7...Valid data display area, 8.
...Data signal generation circuit, 9-...Data display mode detection circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 4 (A) (Snake) Figure 5 Steel top 1rh-to ear shank 9ε Figure 7

Claims (4)

[Claims] (1) A display panel device in which a light-emitting display medium is interposed between X-Y matrix electrodes arranged in a direction crossing each other, in which the inner side of the electrode group connected to the output end of the data-side drive circuit is connected to the data-side electrodes and The outside is used as a data-side border electrode, the inside of the electrode group connected to the output end of the scanning-side drive circuit is used as a scanning-side electrode, and the outside is used as a scanning-side border electrode, and a border signal generation circuit is provided to control the drive output to the border electrode. A border control signal from the above is interpolated into a logic control signal of each drive circuit, and the display area is divided into a first display area displayed by the data side electrode and the scanning side electrode and a second display area displayed by the border electrode. A matrix display panel device comprising: a matrix display panel device, characterized in that the second display area displays a full-scale luminescent display in a positive display mode. (2) Total number of border electrodes connected to the data side drive circuit (m)
On the other hand, regarding the border control signal interpolated into the logic control signal of the data side drive circuit, an interpolation signal for m/2 clocks is interpolated at the rear end of one scanning period where the logic control signal does not exist. A matrix display panel device according to claim 1. (3) Regarding the border control signal to be interpolated to the logic control signal of the scanning side driving circuit for the total number n of border electrodes connected to the scanning side driving circuit, the interpolated signal for n/2 clocks is added to the logic control signal. 2. The matrix display panel device according to claim 1, wherein the matrix display panel device is interpolated at the front end of one field period in which no field period exists. (4) Total number of border electrodes connected to the data side drive circuit (m)
Regarding the border control signal interpolated into the logic control signal of the data side drive circuit, an interpolation signal for m/2 clocks is interpolated at the rear end of one scanning period where the logic control signal does not exist, Regarding the border control signal to be interpolated into the logic control signal of the scanning side driving circuit for the total number n of border electrodes connected to the scanning side driving circuit, the interpolated signal for n/2 clocks is divided into 1 times where the logic control signal does not exist.
The matrix display panel device according to claim 1, wherein the matrix display panel device is interpolated at the front end of the field period.