JPS63215235A - Clock reproducing circuit - Google Patents

Abstract

PURPOSE:To always reproduce a clock coincident with a discrimination timing by constituting the titled circuit by a frequency fixed oscillator, an endless phase shifter shifting the phase of the clock from the oscillator, and a detection section detecting the deviation between the clock phase and the discrimination point of time in a demodulation signal identifier. CONSTITUTION:The clock reproducing circuit 20 consists of an oscillator 22 sending the output of a fixed frequency, the endless phase shifter 23 applying phase shift to the output and a phase deviation detection section 21 monitoring the output of the identifier 12 and detecting the deviation between the optimum discrimination point of time in the identifier 12 and the phase of the clock CLK. The phase deviation detection section 21 detects the change in the phase deviations theta1, theta2... between discrimination point of times Tk, Tk+1... and clocks CLTk, CLTk+1... corresponding to them, and the output phase of the oscillator 22 is shifted in the same step as said change. The deviations theta1, theta2... are always cancelled by the said phase shift to make the phase of the clock always coincident with the discrimination point of time. The continuous phase shift as above is realized by the endless phase shifter 23. The signal after equalizing discrimination is used as the control signal for the clock reproduction and the oscillator 22 of the fixed frequency is adopted to attain highly accurate data recovery.

Description

[Detailed Description of the Invention] [Summary] When a discriminator identifies and encodes an analog demodulated signal obtained by demodulating a multilevel CAM signal and outputs a digital signal, a clock for driving the discriminator is A clock regeneration circuit that generates a clock, the circuit comprising: an oscillator with a fixed oscillation frequency;
It consists of an infinite phase shifter that shifts the phase of the clock from the oscillator, and a phase deviation detector that monitors the output of the discriminator and detects the deviation of the clock phase with respect to the discrimination point in the discriminator, By controlling the phase shift amount of the infinite phase shifter according to the deviation, it is possible to reproduce a clock that always matches the identification timing of the discriminator.

[Industrial application field]

The present invention uses multilevel quadrature amplitude modulation (QAM: Quadr.
atureA+wplitude Modulation
n) Generate a clock to be applied to a discriminator that outputs a digital signal by identifying and encoding the I-channel and Q-channel multilevel analog demodulated signals output from the signal demodulation unit at multiple discrimination levels. This invention relates to a clock recovery circuit.

The clock regeneration circuit is BTR (Bit Tia+inHR).
This circuit is also called a "covery" circuit and reproduces a clock component from a multi-level QAM signal. The recovered clock is mainly used as a timing signal to start the discrimination operation in the discriminator each time. This regenerated clock must be in phase with the timing at which the level of the analog demodulated signal should be identified (when the so-called eye pattern is at its widest), but due to changes in line conditions, this cannot always be ensured. Not exclusively.

[Conventional technology]

FIG. 9 shows a conventional clock recovery circuit and an oscillator (VCO) 2 surrounding it. The oscillator 2, detector 4 and low-pass filter 5 form a so-called PLL (Ph
ase I, Ocked Loop). This P
The signal to which L and L should be synchronized is, for example, the I-channel analog demodulated signal ISa, which is full-wave rectified by the full-wave rectifier 3, and the phase of the clock CLK is compared by the detector 4. Obtain the followed clock CLK.

This clock CLK is mainly used as an identification timing signal in the discriminator 12.

In FIG. 9, the periphery of the clock recovery circuit 1 has the following configuration. Reference numeral 10 denotes a data reproducing section, and although only the data reproducing section on the r channel side is specifically shown in the figure, the data reproducing section 17 on the Q channel side has a similar configuration. These data reproducing sections 10 and 17 operate together with the demodulating section 16 and the clock reproducing circuit 1. That is, the multilevel QAM signal (IF multiplied signal Sin is demodulated by the demodulator 16, and baseband ■ channel (in-phase channel) analog demodulated signal ISa and Q channel (orthogonal channel) analog demodulated signal QSa are output. The clock regeneration unit 1 outputs the regenerated clock CLK.

Analog demodulated signals ISa and QSa output from demodulation section 16 are applied to data reproduction sections 10 and 17, respectively. After the analog demodulated signal TSa (the same applies to QSa) is waveform-equalized in the equalization layer 11, the discriminator 1 equipped with an A/D converter 13 has a predetermined number of discrimination levels.
2, the level is identified and encoded, and the channel digital signal I 5d (Q channel digital signal QSd
The same applies to This is reproduced digital data.

In this case, the clock CLK regenerated by the clock regeneration unit 1 is input to the phase shifter 14 in the I channel data regeneration unit 10 (same as the Q channel data regeneration unit 17) and subjected to a phase shift. It is applied to the clock terminal GK of the converter 3 to determine the identification timing. in general,
Since there is a slight shift between the phase of the analog demodulated signal r5a (same as QSa) and the phase of the clock CLK, the phase shifter 14 compensates for the phase shift.

The A/D converter 13 uses its phase compensated clock CLK.
, the level of the analog demodulated signal I 5a (same as for QSa) is identified and encoded using a predetermined identification level to form a digital signal I 5d (same as for QSd). In the following, only the ■ channel system will be explained as an example, but the Q channel system will also be explained in the same way.

The digital signal ISd encoded and outputted by the A/D converter 13 is a digital signal ISd whose input multilevel QAM signal Sin is, for example, 6
In the case of a four-level CAM signal, it is identified as shown in FIG. 7θ. FIG. 10 is a level diagram for explaining a general discrimination operation by an A/D converter, in which the level of the analog demodulated signal ISa is discriminated by eight predetermined discrimination levels.
Then, from the most significant first bit B1 to the least significant third bit B
3 bits up to 3 (23=8> digital signal ISd
Output.

The first bit B1 of the digital signal ISd is a bit code that is identified and encoded by the identification level LIO that subtracts the entire amplitude of the analog demodulated signal ISa, and is a bit code that is identified and encoded by the identification level LIO that subtracts the entire amplitude of the analog demodulated signal ISa. It also serves as a polarity signal that separates the signal to the side (0).

The second bit B2 is a discrimination level L21 . T, is the bit code identified and encoded by 22.

The third bit B3 is the identification level L21. which defines the second bit B2. Identification level L211, 1, 212, I, 221, L22 which further increases the value divided by L22 to A
2 is a bit code identified and encoded.

The A/D converter 13 converts the fourth bit B4 (10th bit) which is one bit lower than the third bit B3 of the digital signal ISd.
(only one location is shown in the figure) is output as the identification error signal 8 (FIG. 9). The signal ε can be used as a control signal during synchronization pull-in.

Now, control for making the phase of the clock CLK that starts the A/D converter 13 coincide with the timing at which the level of the analog demodulated signal ISa should be identified (identification time point in FIG. 10) is given by the clock regenerating section 1. Regenerated clock CL
This is done by adjusting K by adjusting resistor 15 of manual phase shifter 14. Alternatively, the equalization layer 11 may be adjusted to move the identification time point to match the phase of the clock CLK.

[Problem that the invention seeks to solve]

As shown in FIG. 9, the conventional clock recovery circuit 1 obtains the clock CLK based on the baseband signal immediately after demodulating the multilevel QAM signal Sin, that is, the analog demodulated signal ISa. Therefore, the clock CLK is regenerated while being affected by the line status.

As a result, it becomes difficult to match the phase of the clock CL K with high accuracy to the identification time point shown in Fig. 10, and the quality of the clock deteriorates due to fading, for example, and highly accurate data reproduction may not be possible. There is a first problem. Furthermore, since the voltage-controlled oscillator 2 is used, there is a second problem that the clock phase cannot be controlled with high accuracy. Furthermore, there is a third problem of inconvenience due to the use of the manual phase shifter I4.

The present invention was made in view of the above problems, and an object of the present invention is to provide a clock recovery circuit that does not use a baseband signal, a voltage-controlled oscillator, or a manual phase shifter. It is something to do.

[Means for solving problems]

FIG. 1 is a diagram showing a basic configuration block of a clock recovery circuit according to the present invention and its surroundings. In this figure, the clock regeneration circuit 20 includes an oscillator 22 that sends out a fixed frequency output, and an infinite phase shifter 23 that applies a phase shift to the output.
and a phase deviation detection unit 2 that monitors the output of the discriminator 12 and detects the deviation between the optimum identification time point in the discriminator 12 and the phase of the clock CLK, and adjusts the phase according to the detected deviation. The amount of phase shift of the device 23 is changed.

[For production]

FIG. 2 is a timing diagram for explaining the operating principle of the present invention, in which the eye pattern sequence of FIG.
rk,...T7. One aspect of the present invention uses a fixed frequency oscillator 22 instead of a voltage controlled oscillator. In this case, each identification time point T3゜Tll+1 1
In reality, it is impossible for the period (tl) in which Ti++z... appears to completely match the period (I2) of the output of the oscillator 22. Then, a beat corresponding to the difference (tl--I2) between the period (tl) and the period (I2) will appear. This beat corresponds to each identification time Tv+”rk41
+Th+2... and the corresponding clocks CLK+=, CLKh-+, CLK+1
．． This phase deviation appears as a phase deviation (θ) with respect to
(or the negative (left) side in the figure). Then, the phase deviation, which was zero at the identification time Tk, becomes zero again after a certain period of time, for example, at the identification time T, and this is repeated. Therefore, first, the phase deviation detection section 21 detects the phase deviation θ1.

Detect changes in θ2... Then, the phase of the output of the oscillator 22 is shifted in step with the change in this phase deviation. This phase shift causes θ1.

Always cancel θ2..., CLKk, +, CI
, Kk-z... always Ti+++ + Tl
It can be matched with I42... Such a continuous phase shift can be easily realized by the infinite phase shifter 23. ' Thus, as in the conventional case, the analog demodulated signal Sa immediately after demodulation
is not used as a control source. In other words, since the signal that has been waveform-equalized through the signal generator 11 and identified through the discriminator 12 is used as the control source for the output of the oscillator 22, even if fading or the like occurs, the degree of influence is small. The quality of the clock CLK is improved. Therefore, the identification time point and the phase of the clock CLK can be matched with high precision. Additionally, a highly accurate fixed frequency oscillator can be used. Furthermore, manual phase shifters are also eliminated.

〔Example〕

FIG. 3 is a block diagram showing an embodiment of the clock recovery circuit according to the present invention, and specifically shows the phase deviation detection section 21 in particular. The detection unit 21 includes a slope detector 31 which receives the digital signal Sd as an input and outputs a signal γ representing the slope of change in the analog demodulated signal Sa, and a slope detector 31 which receives the digital signal Sd as an input and outputs a signal γ representing the slope of change in the analog demodulated signal Sa, and receives the signal T and the identification error signal ε as inputs and receives the identification time ( A lead/lag determiner 32 outputs a signal θ indicating an advanced phase or a delayed phase with respect to FIG. 10).

The signal θ changes the amount of phase shift of the infinite phase shifter 23, so that the output of the oscillator 22 becomes a clock CLK having a phase that matches each identification time point.

The deviation detection section 21 generates the signal θ, and the principle of generating the signal θ is as follows.

FIG. 4 is a diagram showing a signal chart for explaining the principle of detecting the deviation between the clock phase and the identification time point. In this figure, the horizontal axis indicates time t, and the vertical direction indicates the level of signal point P. In the case of 64-value QAM, the level is the lowest level ■
There are eight levels ranging from ■ to the highest level ■. Also, the time axis t
Let three consecutive identification time points be T-+, To and Te.
1, and observe the transition of the analog demodulated signal Sa in time series.

However, this observation is not performed directly on the signal Sa, but is performed using the signal Sd as input.

Then, for example, a, b, and C in the figure are obtained as the signal modes of the signal Sa, and many other signal modes (not shown) are obtained. Specifically, signal mode a
In signal mode b, a signal Sa with a positive slope passing through level ■ is shown, and in signal mode b, a signal Sa with a negative slope passing through level ■ is shown.

Signal mode C indicates a signal Sa with an unknown slope. Note that the lowest level ■ corresponds to the code "000", and the highest level ■ corresponds to the code "111".

Based on such slope (positive, negative) information and the positive/negative polarity information of the identification error signal ε, it can be determined whether the phase of the clock cr7 is advanced or delayed. Figure 5 is a level chart showing the principle of detecting the lead phase or lag phase of the clock.
The three time series T-+, To and T41 and the signal mode a shown as an example are the same as shown in FIG. Discrimination level scale of discrimination error signal ε. If the signal point P is represented by 3 bits, the threshold value (r, 0) is used to determine the fourth bit "10" which is one bit lower.

According to the example of FIG. 5, since the slope of the analog demodulated signal Sa is positive, if the signal ε is positive (+), the clock C
The phase of LK is determined to be delayed, and conversely, the signal ε is negative (
-), it is determined that the phase is leading. In the case of signal mode b, although not shown, a determination opposite to the above is made.

The above-mentioned principle of detecting the leading phase or the lagging phase of the clock is reliably established when the so-called eye pattern is well opened. If the eye pattern is distorted, for example, when fading occurs, the following detection principle may be adopted. When the eye pattern collapses, the reliability of the signal point itself and the signal ε itself is lost, so a specific signal mode as described above is set in advance, and only the analog demodulated signal Sa that matches the specific signal mode is used. Extract this and use it as the clock phase judgment 8II.
used for

FIG. 6 is a diagram showing the signal mode used when the line condition is poor (serious error), and corresponds to FIG. 4. Under this bad situation, the four signal modes I, II, and
Only the analog demodulated signal Sa that matches III and ■ is targeted. It is sufficient to target at least one of these four types, but if all four types are targeted, more accurate lock phase matching becomes possible. Referring to FIG. 6 and FIG. 5, the lock phase can be determined as follows.

In the above table, + and - are symbols representing positive and negative, respectively.

For example, under signal mode I, if the slope is positive (+) and the polarity of the identification error signal ε is positive (+), the clock phase is delayed. Further, under signal mode (2), if the slope is positive (+) and the polarity of ε is negative (-), the clock phase is advanced. When the line condition is poor, assume that the eye pattern for identifying each signal point P in Figure 6 is almost completely collapsed, and first select the highest level signal point (■) or the lowest level signal point (■). We will focus on only the signal Sa passing through. No matter how bad the line condition is, the signal point (■)
This takes into account the fact that a signal point will never appear higher than the signal point (■) and that a signal point will never appear lower than the signal point (■). Furthermore, regarding the polarity of the identification error signal ε to be used, no matter how bad the line condition is, the positive polarity above the highest level ■ (
+) can take a value other than positive, and the negative polarity (-) below the lowest level ■ cannot take a value other than negative.As the polarity information of ε, signal mode 1 ．． Only positive is used for IT, and only negative is used for signal mode III and rV. In short, clock phase control is performed by collecting only the most reliable information. Looking at the sign of the slope, even though the conditions in the table above are satisfied, signal modes ■ and ■ have an extremely high probability of having a positive linear slope, and signal modes ■ and ■ have an extremely high probability of having a negative primary slope. It needs to be high. For this purpose, it is desirable to impose the following conditions. In other words, signal mode I passes through a signal point at a level lower than level ■, passes through a signal point at the highest level (■), and reaches a signal point at a level higher than level ■. In signal mode ■, the signal passes through the signal point at the highest level, passes through the signal point (■) at the highest level, and reaches the signal point at a level lower than level ■. It passes through the signal point (■) and reaches a signal point at a higher level than level ■, and the signal mode ■ is level ■.
It is assumed that the signal passes through a signal point at a higher level, passes through a signal point at the lowest level (■), and reaches a signal point at a level lower than level ■.

FIG. 7 is a block diagram showing an example of a practical configuration of a clock recovery circuit based on the present invention.
3) consists of a first tilt detector 311 and also has a second tilt detector 312. The first slope detector 311 detects whether the slope is positive or negative only for the analog demodulated signal Sa in which monotonically increasing (a) and monotonically decreasing (b) are shown in FIG. When this detector 311 alone cannot cope with the deterioration of the line condition, a second slope detector 312 is added.
It is preferable to provide The second tilt detector 312
Tilt detection is performed in the signal mode explained in the figure. These first and second tilt detectors 311 and 312 are selectively driven depending on line conditions. The line condition is determined by detecting the data error rate by the error detector 24. When the line condition is good (data error rate is small), the first slope detector 311 is driven; large) drives the second tilt detector 312.

FIG. 8 is a circuit diagram showing a specific example of a clock recovery circuit based on the present invention. In this figure, the first tilt detector 311 and the second tilt detector 312 in FIG. It has 44. Further, the lead/lag determiner 32 in FIG. 7 is realized by an exclusive OR gate 63.

First, we will explain what happens when the line condition is bad.

The fourth signal Sd passes through both the delay circuits 43 and 44.
A signal corresponding to the signal point at the identification time T-8 in the figure is obtained, and the signal Sd that passes only through the delay circuit 44 and the signal Sd that does not pass through the delay circuit at all are obtained at the identification times T0, T, 1 in the figure. The signals corresponding to the signal points at are obtained respectively. That is, information representing various signal modes of the analog demodulated signal Sa is applied to the input of the ROM 42. RO? ! 42 stores in advance various information corresponding to this information. For example, if it is determined from the information input to the RUM 42 that the signal mode ■ shown in FIG. Output showing ``1
” and an output “1” indicating that only the positive polarity of the identification error signal ε should be used from X, respectively.

Note that when the signal is not a specific mode signal, the Z output becomes 0'' (invalid), and the contents of the signal holder 53 remain unchanged.

The output X of the ROM 42 indicates whether either signal mode I or H in FIG. 6 appears ("1") or signal mode ■.

If either of (2) appears, it indicates "0"), and if the former, only the positive polarity signal ε ("1") is passed, and if the latter, only the negative polarity signal ε (0") is passed through the selector 52. consists of a decoder 61 as shown in the figure, and inputs "1" when the human power (E, F) is "1.1" and "0" when it is "0.0" to the lead/lag determiner 32. It consists of an exclusive OR gate 63, with a bit "1" or "0" representing the positive or negative slope of the signal, and a bit "
Exclusive OR with ``1'' or ``0'' to determine the clock phase lead (1'') or lag (``O'') shown in the table above.
is sent to the signal holder 53.

This consists of a D-flip-flop 62 as shown,
The output of the gate 63 is passed through the infinite phase shifter 23 depending on the output of the valid/invalid instruction line 55, or is supplied to the infinite phase shifter 23 while the previous one is held.

Next, we will explain the case when the line condition is good.In this case, it is not enough to use only the signals of the specific mode shown in Fig. 6, but to use signal modes a, b, etc. shown in Fig. 4. Control may be performed using the ROM 41. In this way, line conditions can be dealt with flexibly, and timing control over a wide range of lock phases can be realized. Whether ROM 41 or ROM 42 is used depends on the line status. For this purpose, a pseudo error detector 24 is also provided to determine whether the line condition is good or bad. The detector 24 receives, for example, the first bit ε1 of the identification error signal ε and its lower second bit ε2, and detects the error rate. If the error rate falls below, for example, io-', it is assumed that the line condition has deteriorated, and a switching signal SW is output. This signal SW switches the contacts of the switch 51 and drives the ROM 41 and ROM 42 alternatively. The ROM 41 has the signal mode (a,
b, etc.), a signal indicating validity/invalidity is sent to the Z' output (invalidity is in the case of signal mode C in FIG. 4). When valid (signal modes a and b in FIG. 4), a signal representing the positive/negative of the slope i is sent out with a small output of Y'.

When the error rate becomes, for example, 10-3 or more, a switching signal SW is sent out to switch the contact of the switch 51 from the lower contact to the upper contact in the figure, and on the other hand, from the ROM 41 to the ROM 42.
Switch the drive to . This is done by applying a signal SW to the enable terminal EN of each ROM (ROM 41 is equipped with an inverter). When the signal SW disappears due to improvement in the line condition, the ROM 41 is driven again and the contact of the switch 51 is also switched to the lower side.

The infinite phase shifter 23, which is an important component of the present invention, is controlled by receiving the "1" and "0" outputs from the signal holder 53 mentioned above.The function of this phase shifter 23 is to The input of the oscillator 23 (output from the oscillator 22) is sinθ, and the phase shifter 2
If the output of
Z + qZ = l, p + a3 in tx, q*
c, os cx).

Sin θ in the above equation is the output of the oscillator 22 that passes through the π/2 hybrid 77 in FIG. Cos θ in the above equation is the output of the oscillator 22 which is transferred and summed by π/2 in the π/2 hybrid 77, and becomes pc and os θ in the multiplier 75. Therefore, how to change the phase shift amount α is p.

It is determined by the value of q. (J of these p, q changes based on the value of the up/down (U/D) counter 71, and the value of the counter 71 is the output (“1”,
'0''), that is, depending on the negative or positive phase deviation mentioned above.

Furthermore, the value that the counter 71 increases or decreases is stored in the ROM.
72 address. The ROM 72 stores various pre-calculated numerical values for phase shift control. That is, according to the output of the counter 71, and pZ
The values of p and q that satisfy +qZ = l are calculated and stored as digital values.

These digital values are converted to a digital/analog converter (D
/A) It is converted into an analog value at 73 and 74 and applied to multipliers 75 and 76. In this way, a phase shift amount corresponding to the phase deviation is added to the output of the oscillator 22 to obtain the desired clock CLK, which is further applied to the clock terminal of the discriminator 12.

〔Effect of the invention〕

As described above, according to the present invention, since the signal after equalization identification is used as a control signal for clock reproduction and the fixed frequency oscillator 22 is employed, highly accurate data reproduction is possible. It also makes it possible to eliminate the conventional manual phase shifter and automate it.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration block of a clock recovery circuit based on the present invention and its surroundings. FIG. 2 is a timing diagram for explaining the operating principle of the present invention. FIG. 3 is a clock recovery circuit based on the present invention. A block diagram showing one embodiment; Fig. 4 is a signal chart for explaining the principle of detecting the difference between the clock phase and the identification time; Fig. 5 is a diagram showing the detection of the leading or lagging phase of the clock. A level chart showing the principle; FIG. 6 is a diagram showing signal modes used in poor line conditions (serious errors); FIG. 7 is a block diagram showing a practical configuration example of a clock recovery circuit based on the present invention; FIG. 8 is a circuit diagram showing a specific example of a clock recovery circuit based on the present invention, FIG. 9 is a diagram showing a conventional clock recovery circuit and its peripheral circuits, and FIG. 10 is a general identification using an A/D converter. This is a level diagram for explaining the operation. 12... Discriminator, 16... Demodulator, 20...
... Clock regeneration circuit, 21 ... Phase deviation detection section, 22 ... Oscillator, 23 ... Infinite phase shifter, 31
... Tilt detector, 32 ... Advance/delay determiner, 31
DESCRIPTION OF SYMBOLS 1... 1st inclination detector, 312... 2nd inclination detector, 71... Up/down counter, 72... Read only memory, 75, 76... Multiplier, 77. ...π/2 hybrid.

Claims (1)

[Claims] 1. The analog demodulated signal (Sa) obtained by demodulating the multilevel orthogonal amplitude modulation signal (Sin) is identified at a predetermined number of identification levels, and corresponds to the identified signal point (P). This circuit supplies a clock (CLK) for driving the discriminator to the discriminator (12) which encodes the digital signal (Sd) into a digital signal (Sd) and sends out the discrimination error signal (ε). In a clock regeneration circuit comprising an oscillator that generates a clock (CLK) whose phase coincides with the timing for identifying the level of (Sa), that is, the time of identification, the oscillator comprises a fixed frequency oscillator (22), and further An infinite phase shifter (23) that adds a phase shift to the output of the oscillator (22), and a clock (C) that monitors the output of the discriminator (12) for the discriminator (12)
A phase deviation detection unit (21) is provided to detect a phase deviation of the phase shifter (21), and an infinite phase shifter (2
3) A clock regeneration circuit that regenerates a clock (CLK) by changing the amount of phase shift. 2. The phase deviation detection unit (21) detects three consecutive identification time points (T_-_1, T_0, T_
A slope detector (31) that sequentially receives the digital signal (Sd) obtained in +_1) and detects the positive or negative of the slope of the corresponding analog demodulated signal (Sa), and a slope detector (31) that detects the positive or negative of the slope of the detected slope and the identification error signal ( a lead/lag determiner (32) that determines whether the phase of the clock (CLK) is ahead or behind the identified time point (T_0) based on the combination of positive and negative polarities of ε);
2. The clock recovery circuit according to claim 1, wherein the clock regeneration circuit is configured to change the phase shift amount of the infinite phase shifter (23) to the negative side or the positive side depending on the lead or lag. 3. Claim 2, wherein the slope detector (31) includes a first slope detector (311) that detects whether the slope is positive or negative only for monotonically increasing or monotonically decreasing analog demodulated signals (Sa). Clock regeneration circuit described in section. 4. The tilt detector (31) further connects the second tilt detector (3
12), and the analog demodulated signal (Sa) identifies the signal point (P) at the highest level or the lowest level (T_
The sign of the slope is detected only for the analog demodulated signal (Sa) passing at 0), and the discrimination error signal (ε ) is input to the lead/lag determiner (32) as a valid polarity only when the polarity is positive or negative, respectively, and the discrimination error signal (ε) is monitored to generate a digital signal (Sd).
an error detector (24) for detecting a data error rate of
the first one depending on the decrease or increase of the data error rate
tilt detector (311) or the second tilt detector (31
3. The clock regeneration circuit according to claim 3, which selectively drives 2). 5. The infinite phase shifter (23) includes an up/down counter (71) whose count value increases or decreases depending on whether the detected phase deviation is negative or positive, and various pre-calculated phase shift control devices. A read-only memory (72) stores the numerical values (p, q) and outputs the corresponding numerical values (p, q) according to the count output of the up/down counter (71); A multiplier (75) and a multiplier (76) each receive a numerical value (q) as an analog quantity at one input terminal, and the other input terminal of the multiplier (75, 76) receives one as it is and the other one as π. /2 phase shifted oscillator (
π/2 hybrid (
77), and the clock (CLK) is the composite output of the multipliers (75, 76).