JPS63204386A - Electronic equipment capable of attaching/detaching external memory - Google Patents
Electronic equipment capable of attaching/detaching external memoryInfo
- Publication number
- JPS63204386A JPS63204386A JP62036140A JP3614087A JPS63204386A JP S63204386 A JPS63204386 A JP S63204386A JP 62036140 A JP62036140 A JP 62036140A JP 3614087 A JP3614087 A JP 3614087A JP S63204386 A JPS63204386 A JP S63204386A
- Authority
- JP
- Japan
- Prior art keywords
- external memory
- buffer
- signal line
- state
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 title claims abstract description 35
- 230000008878 coupling Effects 0.000 description 10
- 238000010168 coupling process Methods 0.000 description 10
- 238000005859 coupling reaction Methods 0.000 description 10
- 238000001514 detection method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 1
- 244000145845 chattering Species 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は外部メモリを着脱可能な電子機器に関するもの
で、特に、外部メモリとのデータの受授をバッファを介
して行う外部メモリを着脱可能な電子機器に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an electronic device with a removable external memory, and particularly to an electronic device with a removable external memory that exchanges data with the external memory via a buffer. related to electronic equipment.
[従来の技術]
従来から着脱可能な外部メモリとして、例えばフォント
カートリッジ、増設メモリバック、メモリカード等が用
いられてきた。これらメモリは第4図に示す如く記録装
置内部の制御回路と電気的に直接接続されている。[Prior Art] For example, font cartridges, additional memory bags, memory cards, etc. have been used as removable external memories. These memories are directly electrically connected to a control circuit inside the recording apparatus, as shown in FIG.
[発明が解決しようとする問題点]
しかしながらこの場合、電源投入の状態での着脱のさい
、結合部から発生するチャタリング等のノイズにより1
本体の制御回路が悪影響を受けて制御回路の誤動作もし
くは暴走と言った問題が発生している。この対策として
は通常電源投入状態でのメモリの着脱を禁止することが
行われているが、これはユーザーにとっては使い勝手が
悪くまた電源投入の状態で誤まってメモリの着脱を行っ
た場合、制御回路が暴走し機器が故障するという問題が
起っている。[Problems to be Solved by the Invention] However, in this case, when the power is turned on and the connection is performed, noise such as chattering generated from the joint may cause
The control circuit of the main unit is adversely affected, causing problems such as malfunction or runaway of the control circuit. A countermeasure against this problem is to prohibit the installation or removal of memory while the power is on, but this is inconvenient for the user, and if the memory is accidentally installed or removed while the power is on, the control Problems have arisen in which circuits run out of control and equipment breaks down.
[問題点を解決する為の手段]
この問題を解決する為に1本発明は、外部メモリの装着
手段と電子機器本体の間にバッツァを設け、外部メモリ
装着手段の状態に従って、該バッファを否動作状態とす
る制御手段を備える。[Means for solving the problem] In order to solve this problem, the present invention provides a buffer between the external memory mounting means and the main body of the electronic device, and disables or disables the buffer according to the state of the external memory mounting means. It is provided with a control means for setting it in an operating state.
[実施例] 本発明の実施例を以下図面を用いて説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.
第1図は本発明におけるブロック図である。ここで1は
外部メモリ、2はロック機能を有する結合ユニット、3
は内部バス9と外部バス8を切り分けるためのバッファ
である。内部バス9と外部バス8にはデータバス、アド
レスバス・メモリ制御信号が含まれる。4は制御回路で
外部メモリlと・データのやりとりを行ったり電子機器
全体の制御を行う、この制御回路は第2図のフローチャ
ートに従った制御プログラムを格納するROWを有する
。7は結合ユニット2に含まれるロック検出SWの信号
線である。FIG. 1 is a block diagram of the present invention. Here, 1 is an external memory, 2 is a coupling unit with a lock function, and 3
is a buffer for separating the internal bus 9 and external bus 8. Internal bus 9 and external bus 8 include a data bus, address bus, and memory control signals. Reference numeral 4 denotes a control circuit that exchanges data with the external memory 1 and controls the entire electronic device.This control circuit has a ROW that stores a control program according to the flowchart of FIG. 7 is a signal line of a lock detection SW included in the coupling unit 2.
制御回路4は結合ユニット2のロック検出SWからの信
号線7の状態を検出し、結合ユニット2がロック状態で
あるならば、バッファ制御信号線5を動作状態とし、ロ
ック状態でない場合、バッファ制御信号線5を否動作状
態とする。このバッファ制御信号線5からの信号に従っ
て、バッファ3は動作状態になったり、否動作状態にな
ったりする。The control circuit 4 detects the state of the signal line 7 from the lock detection SW of the coupling unit 2, and if the coupling unit 2 is in the locked state, sets the buffer control signal line 5 to the operating state, and if it is not in the locked state, sets the buffer control signal line 5 to the operating state. The signal line 5 is brought into a non-operating state. According to the signal from the buffer control signal line 5, the buffer 3 is placed into an active state or a non-active state.
6は結合ユニット2と外部メモリlの結合状態を検出す
る信号である。システムの信頼性を上げるため、制御回
路4はバッファ制御信号線5を制御するにあたって、ロ
ック検出信号7と結合検出信号6とのアンド状態を検出
して、バッファ制御信号5を動作状態とする様、制御す
ることが考えられる。第2図に本発明における制御のフ
ローチャートを示す。6 is a signal for detecting the coupling state between the coupling unit 2 and the external memory l. In order to increase the reliability of the system, the control circuit 4 detects an AND state between the lock detection signal 7 and the coupling detection signal 6 when controlling the buffer control signal line 5, and sets the buffer control signal 5 to the operating state. , it is conceivable to control. FIG. 2 shows a flowchart of control in the present invention.
ステップSlでは、制御回路4のイニシャルセットを行
いステップS2において、ロック検出信号7からの信号
によってロック状態か否かを判断する。In step Sl, the control circuit 4 is initialized, and in step S2, it is determined whether or not it is in a locked state based on a signal from the lock detection signal 7.
ロック状態であれば、ステップS5においてバッファ制
御信号線5によりてバッファ3を動作状態に即ち、外部
メモリ1と制御回路4との間で外部バス8、内部バス9
を介してデータの交信を可能状態にし、ステップS6に
移項する。ステップS6では、一般の制御を行う。If it is in the locked state, in step S5, the buffer control signal line 5 puts the buffer 3 into the operating state, that is, the external bus 8 and internal bus 9 are connected between the external memory 1 and the control circuit 4.
Data communication is made possible through the step S6. In step S6, general control is performed.
一方、ステップS2でロック状態でないならばステップ
S3へ移項し、外部メモリエラー処理を行う、ここでは
、バッファ制御信号線5によってバッファ3を否動作状
態とし、警告としてCRT!Oにエラー表示をしたり、
ブザー21を鳴す、そしてステップS4において、ロッ
ク検出信号7からの信号によってロック状態か否かを判
別し、ロック状態になるまてステップS3.34を繰り
返す、そして、ロック状態になるとステップS5に移項
する。On the other hand, if it is not in the locked state in step S2, the process moves to step S3 and external memory error processing is performed.Here, the buffer 3 is set to a non-operating state by the buffer control signal line 5, and the CRT! Display an error on O,
The buzzer 21 is sounded, and in step S4, it is determined whether or not the lock is in the lock state based on the signal from the lock detection signal 7. Steps S3 and 34 are repeated until the lock is reached, and when the lock is reached, the process proceeds to step S5. Transfer.
第3図に、本発明の構成例を示す0図中lOは電子機器
の外装、12は外部メモリlの収納カバー、16は操作
つまみである。外部メモリlの着脱時には収納カバー1
2はカバーガイド11にそって上部に押し上げられる。FIG. 3 shows an example of the configuration of the present invention. In FIG. 3, lO is the exterior of the electronic device, 12 is a storage cover for the external memory l, and 16 is an operation knob. When installing or removing external memory l, remove storage cover 1.
2 is pushed upward along the cover guide 11.
このときスイッチ13は、カバー12が押し上げられる
動作にともない、0FF(またはON)する極配置し、
ロック検出を行う、15は、メモリカート用コネクタ、
14はメインPCBである。At this time, the switch 13 is arranged as a pole that turns OFF (or ON) as the cover 12 is pushed up,
15 is a memory cart connector that performs lock detection;
14 is the main PCB.
以上の構成によって、メモリカードlの着脱を行う場合
、必ずメモリカードの収納カバー12を開けることによ
り、またロック検出はカバーの開閉に連動して行われる
ことによりメモリカードの着脱時に外部バスと内部バス
を切り分けることが可能となる。With the above configuration, when inserting or removing the memory card l, the memory card storage cover 12 must be opened, and lock detection is performed in conjunction with the opening and closing of the cover, so that when the memory card is inserted or removed, the external bus and internal It becomes possible to separate the bus.
なお本発明において、第1図に示す結合ユニットは第3
図にて収納カバー12、カバ一つまみ16.カバースイ
ッチ13、カバーガイド11、メモリカードコネクタ1
5により構成される。In the present invention, the coupling unit shown in FIG.
In the figure, a storage cover 12, a pinch of cover 16. Cover switch 13, cover guide 11, memory card connector 1
Consisting of 5.
[他の実施例1
信頼性の向上のため、パスラインを分離するだけでなく
、電源も断とする様1例えば外部バスを切り離した後、
外部メモリの電源をトランジスタ等を用いてOFFする
ことが考えられる。[Other Embodiment 1] In order to improve reliability, in addition to isolating the pass lines, the power supply is also cut off. For example, after disconnecting the external bus,
It is conceivable to turn off the power to the external memory using a transistor or the like.
[効果]
電源投入状態での外部メモリ着脱に関するトラブルを防
止することが可能となる。[Effect] It is possible to prevent troubles related to attaching and detaching external memory while the power is on.
第1図は本発明におけるブロック図、
第2図は本発明の制御手順を示すフローチャート、
第3図は本発明の構成図、
第4図は従来例におけるブロック図。
図中1は外部メモリ、2は結合ユニット、4は制御回路
、6は結合検出信号、9は内部バスである。
冨20FIG. 1 is a block diagram of the present invention, FIG. 2 is a flowchart showing a control procedure of the present invention, FIG. 3 is a configuration diagram of the present invention, and FIG. 4 is a block diagram of a conventional example. In the figure, 1 is an external memory, 2 is a coupling unit, 4 is a control circuit, 6 is a coupling detection signal, and 9 is an internal bus. Tomi 20
Claims (1)
段と、 前記外部メモリ装着手段に装着された外部メモリとデー
タの受授を行なう電子機器本体と、前記外部メモリ装着
手段と前記電子機器本体との間に設けられるバツフア手
段と、 前記外部メモリ装着手段の状態に従って前記バツフア手
段を否動作状態とする制御手段とを有することを特徴と
する外部メモリを着脱可能な電子機器。[Scope of Claims] External memory mounting means to which an external memory can be attached and removed; an electronic device main body that exchanges data with the external memory mounted on the external memory mounting means; and the external memory mounting means and the 1. An electronic device to which an external memory can be attached or removed, comprising: a buffer means provided between the electronic device body and a control means for setting the buffer means in a non-operating state according to a state of the external memory mounting means.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62036140A JPS63204386A (en) | 1987-02-19 | 1987-02-19 | Electronic equipment capable of attaching/detaching external memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62036140A JPS63204386A (en) | 1987-02-19 | 1987-02-19 | Electronic equipment capable of attaching/detaching external memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63204386A true JPS63204386A (en) | 1988-08-24 |
Family
ID=12461481
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62036140A Pending JPS63204386A (en) | 1987-02-19 | 1987-02-19 | Electronic equipment capable of attaching/detaching external memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63204386A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6491226B1 (en) | 1998-08-24 | 2002-12-10 | Nec Infrontia Corporation | Method and apparatus for preventing extraction of card-shaped functional device for information processing apparatus, and recording medium storing program for realizing extraction preventing operation on computer |
-
1987
- 1987-02-19 JP JP62036140A patent/JPS63204386A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6491226B1 (en) | 1998-08-24 | 2002-12-10 | Nec Infrontia Corporation | Method and apparatus for preventing extraction of card-shaped functional device for information processing apparatus, and recording medium storing program for realizing extraction preventing operation on computer |
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