JPS63204173A - Digital signal test system - Google Patents

Abstract

PURPOSE:To achieve a higher accuracy to judging propriety, by supplying a low speed digital signal from a signal generation means. CONSTITUTION:In a printed circuit board 1b, an operation program section 11a is activated by a CPU 10a and high and low speed digital signals (a) and (b) are outputted by high and low speed signal generation circuits 12a and 13a. The signal (a) is sent to a tester 2b to count the number (n) of pulses with a pulse counting circuit 25. The signal (b) is sent to the device 2b, a measuring timing is specified with a sample window generation circuit 21 based on a synchronous signal (c) and a sampling signal (d) is sent to a memory 22, an output signal (e) of which is sent to a comparative decision circuit 24. A reference output F is sent to the circuit 24 synchronizing the signal (e) and the results of decision on propriety are outputted. The number (n) of pulses is sent to a comparative decision circuit 27 and a reference output N is sent to the circuit 27 synchronizing the number (n) of pulses to output the results of decision on propriety. When the results of judgement of the circuit 24 and 27 are both good, the test object is accepted. This achieves a higher accuracy of judging the propriety of a high-speed digital signal.

Description

[Detailed Description of the Invention] [Summary] A test method for determining the quality of high-speed digital signals output from a printed circuit board unit etc. equipped with a central processing unit, which includes a signal generating means for generating low-speed digital signals. Automatic testing is possible by supplying low-speed digital signals to the device under test.

(Industrial Application Field) The present invention relates to a printed board unit (hereinafter referred to as a printed board) equipped with a central processing unit (hereinafter referred to as a CPU).
The present invention relates to a test method for high-speed digital signals output from a computer, and in particular to a digital signal test method that can automate the test.

BACKGROUND ART In recent years, printed boards on which various electronic components such as micro CPUs are mounted have been used in control units of electronic devices, and operational tests of printed boards are conducted during manufacturing.

Digital signals output from printed circuit boards are becoming faster and faster, and testing methods that visually judge the signals on a display (hereinafter referred to as CRT) have a limited accuracy. A possible method is desired.

[Conventional technology]

In FIG. 4, 1a is a printed board and is the object to be tested.

IO is a CPU, 11 is an operation program section, 12 is a digital signal generation circuit (hereinafter referred to as a signal generation circuit), 13 is a connection section, 2a is a printed board of the same type as the printed board 1a, or a printed board from an actual device to be mounted. The test device from which 20 is removed indicates a CRT.

Therefore, when testing the printed board 1a, the device 2a and the printed board 1a are connected at the connection part 13 as shown in the figure, and the CP
The operation program unit 11 is operated by Ul0, and the signal generation circuit 12 is caused to output a digital signal. The output signal is displayed as a signal waveform etc. on the CRT 20 of the device 2a, and the operator determines the quality by looking at the signal waveform etc. displayed on the screen.

[Problem that the invention seeks to solve]

In recent years, the speed of digital signals handled by printed circuit boards has become significantly faster (e.g., about 4 lnS), and conventional testing methods that visually judge signal waveforms on the screen cannot be used to determine pass/fail. There are problems with this method, such as the unavoidable loss of accuracy, the inability to automatically determine pass/fail in tests using actual equipment, and the lack of versatility since different models use different types of printed circuit boards.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, 1 is a test object equipped with an operation processing unit and a high-speed digital signal generation means, 2 is a test device, and 3 is a generator that generates a low-speed digital signal (No. 3 generation means).

Therefore, the device under test 1 is configured to supply a low-speed digital signal generated from the signal generating means 3.

[Effect]

When the low-speed digital signal generated from the signal generating means 3 is supplied to the test object 1, the signal output from the test object 1 becomes a slow and simplified signal, which makes it easy for the test device 2 to determine pass/fail. Automatic judgment will also be possible.

〔Example〕

The present invention will be described in detail with reference to FIGS. 2 and 3.

The same reference numerals indicate the same objects throughout the figures. In FIG. 2, parts corresponding to those in FIG. 1 are shown surrounded by a dashed line.

Figure 2 shows the printed board 1b of the test object and the test equipment 2b, and the test equipment 2h is used to generate high-speed digital signals (
For example, a signal of about 40 nS as shown in FIG. 3 (al) is automatically determined.

In the figure, a low-speed digital signal generation circuit (hereinafter referred to as low-speed signal generation circuit) 3a is composed of, for example, a ROM, and stores a test low-speed digital signal generation program. That is, as shown in FIG. 3 (bl), it has a function of generating a simple output signal at low speed (for example, about 40 μs).The ROM is removably installed in a socket provided on the printed board 1b.

In the printed board 1b, 10a is a CPU, lla is an operation program section, and 12a is a high-speed digital signal generation circuit (hereinafter referred to as high-speed signal generation circuit).

In the test device 2b, the sample window generation circuit 2
1 has a function of specifying the measurement timing based on the synchronization signal C sent from the printed board 1b.

The memory 22 is a storage means for storing low-speed digital signals sent from the printed board 1b.

The memory 23 is a storage means in which standard data F to be compared with the output signal e of the memory 22 is stored.

The comparison and determination circuit 24 has a function of comparing and determining the signals e and F sent synchronously from the memories 5 and 6.

The pulse count circuit 25 has a function of counting the number of pulses n of the high speed digital signal a sent from the printed board 1b.

The memory 26 is a storage means in which the number of pulses n is compared with the regulation (iiN force < 8 a).

The comparison and determination circuit 27 has a function of comparing and determining the specified value N of the memory 26 and the number of pulses n counted by the pulse count circuit 25.

Further, the printed board 1b and the test device 2b are connected to the output signal lines 1, 1 . and are connected by output synchronization signal lines 1 and 2.

Since it has such a configuration and function, the operation will be explained next.

(2) First, in the printed board 1b, the CPU 10a operates the operation program section 11a to cause the high-speed signal generation circuit 12a and the low-speed signal generation circuit 3a to output the high-speed digital signal a and the low-speed digital signal S. At this time, for example, the output signal is set to "1°" in units of synchronous signals.
゛、Create a display pattern that switches to "0". This allows sampling several tens of times within one unit of signal.Furthermore, the output signal is set to "1".

Switch “0” and repeat several times.

■High-speed digital signal a is output signal line 17. Test equipment 21) \ sent by pulse callan I circuit 25
The number of pels n is counted.

■Also, the low-speed digital signal is sent to the test equipment 2b via the output signal line L2, and based on the synchronization signal C sent via the output synchronization signal line L2, the sample window generation circuit 21
The measurement timing is designated by , and the sampling signal d is sent to the memory 22 .

(2) The output signal e is sampled by the sampling signal d and sent from the memory 22 to the comparison/judgment circuit 24.

■Synchronizing with the output of the output signal e, the standard (i
ffF is output and sent to the comparison/judgment circuit 24.

(2) The comparison/determination circuit 24 compares the output signal e with the standard value F, and outputs a pass/fail determination result.

(2) On the other hand, the number n of pulses counted by the pulse count circuit 25 is output and sent to the comparison/judgment circuit 27.

■The reference fi is sent from the memory 26 in synchronization with the output of the number of pulses n.
N is output and sent to the comparison/judgment circuit 27.

(2) In the comparison/judgment circuit 24, the number n of pulses and the reference number N are compared, and a quality/failure determination result is output.

[Phase] Then, based on the pass/fail judgment results of ■ and ■, if both are good, it is determined to pass.

In this way, high-speed digital signals can be automatically judged to be good or bad, and can be used universally even when different types of printed boards are used.

In the above example, the case where the low-speed signal generation circuit 3a is installed in the socket of the printed board 1b has been explained, but the low-speed signal generation circuit 3a is installed in, for example, the test equipment 2b, and connected to the printed board 1b via a line to perform low-speed digital A similar effect can be obtained by supplying a signal.

In addition, as explained in the conventional example, the low-speed digital signal generated from the printed board 1b is transferred to the C of the actual device 2a.
The accuracy of visual judgment can also be improved by displaying the information on the RT 20.

〔Effect of the invention〕

As explained above, according to the present invention, (1) the accuracy of high-speed digital signal quality determination can be improved;

■Pass/fail judgment can be performed automatically.

There is an effect.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a schematic diagram showing an embodiment of the present invention, Fig. 3 is an explanation of signals in the embodiment, and Fig. 4 is a block diagram showing a conventional example. be. In the figure, ① is the test object, la and lb are printed boards, and 2.
2b is a test device, 2a is a test device, 3 is a signal generating means, and 3a is a low-speed signal generating circuit.

Claims (2)

[Claims] (1) A device under test (1) equipped with a motion processing unit and high-speed digital signal generation means is connected to a test device (2), and the high-speed digital signal is processed by the motion processing unit and output from the device under test (1). A test system in which a signal is judged pass/fail by the test device (2), further comprising: a signal generating means (3) for generating a low-speed digital signal; A digital signal test method characterized by supplying digital signals. (2) The signal generation means (3) is a storage means for storing a test low-speed digital signal generation program mounted on the test object (1). digital signal test method.