JPS63197282A - Parallel image processor - Google Patents

Abstract

PURPOSE:To prevent the degradation in the processing efficiency of the communications between a host processor and processor unit by transmitting the image data processed parallelly by plural image processor units through plural data transmitting paths. CONSTITUTION:The processor consists of an image memory 5 for planting the image data to be an object of image processing a plurality of image processor units 2-1-2-6, the host processor 1 which is connected to the image memory 5 and which is connected to the plural image processor units 2-1-2-6 through plural data-transmitting paths 3-1-3-6 and interface means 306-309 for transferring the image data before and after for every image processing unit between the host processor 1 and individual image processor units 2-1-2-6 through a plurality of the data transferring paths 3-1-3-6 for each image unit processor. The communications between the host processor and each unit processor are multiplexed to prevent the degradation in the processing efficiency even when plural image processor units are used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel image processing device having a plurality of image processing units.

[Prior Art] In the field of image processing, in view of the enormous amount of data to be processed, data is sometimes processed in parallel by a plurality of image processing units (hereinafter abbreviated as processing units PU).

FIG. 2 is a block diagram illustrating a conventional parallel image processing device. 1 is a host processor, and 2-1 to 2- are PUs that perform parallel processing (hereinafter, these will be collectively referred to as 2).

32-1+3-2, etc. are communication paths for inter-processor communication (hereinafter, these will be collectively referred to as 3), 4 is the host processor's own memory, and 5 is the image and I! Ij
1 is the image memory that holds the filled image, 6 is the image memory 5
7 is the display controller for displaying the data of
, T, 8 is a system bus, and 9 is a display bus.

FIG. 3 is an internal block diagram of the PU 2, in which 201 is a CPU having an inter-processor communication function, 202 is a local memory, and 203 is an internal communication path inside the processor.

FIG. 4 is a diagram illustrating an image to be processed, and 10
represents an image, and 10- and 10-6 represent divided partial images.

Parallel image processing according to a conventional example will be explained using FIG. 2.3.4. First, the image 10 held in the image memory 5 is read out and divided by the host processor 1, and each divided partial image 10-1 to 10-4 is
U2-, -PUI are transmitted to the respective local memories 202 via the communication path 3 (). Next, each PU 2 performs image processing in parallel on the partial images held in each local memory 202 . The results are transferred from the host processor 1 to the image memory 5 via the communication path 3, and the CR,
The results are displayed on T8. This is basic parallel image processing.

[Problems to be Solved by the Invention] There are the following two problems in such a system.

First, it is necessary to perform interprocessor communication when transferring the image to be processed to each Pυ and when transferring the processed image from each PU to the image memory 5, but normally this kind of communication is required. Since the communication path 3 is serially transferred, the communication speed is slow and there is a serious drawback that it takes a lot of time to transfer the image data.

Second, image processing usually involves many neighborhood calculations for pixels to be processed. Therefore, image processing can be completed within each PU except for the boundary area of the partial image. Further, the boundary area can also be processed by performing inter-PU communication via the communication path 3. The amount of communication at this time is small compared to the entire processing time. However, when attempting to rotate an image, for example, it becomes necessary to transfer data of each partial image held by each PU through inter-processor communication and rearrange the pixels. In particular, increase the number of PUs, increase parallelism,
If an attempt is made to increase the speed, the amount of communication between the PUs will increase accordingly, the time required for communication will increase, and processing efficiency will decrease. When similar images are divided and processed and the amount of communication between processors is large, there is a serious problem that it usually takes time.

In other words, if the above problem is summarized, if the processing unit of image processing imposed on each PU is substantially independent between each PU, communication between PUs will not be a problem because there will be less processing in the boundary area. However, communication between the host processor and the PU, which occurs in large quantities at once, becomes a bottleneck in processing efficiency. Conversely, when the unit of image processing is multiple P, such as image rotation,
In the case of spanning between U, communication between each PU becomes a bottleneck in processing efficiency.

Therefore, the present invention has been proposed to solve the above-mentioned problems of the prior art.The purpose of the present invention is to solve the problem that even if a plurality of image processing units are used, communication between the host processor and each processing unit reduces processing efficiency. The object of the present invention is to provide a parallel image processing device that does not become a factor.

[Means for Solving the Problems] The configuration of the present invention for achieving the above-mentioned problems includes an image memory that stores image data to be image processed, a plurality of image processing units that perform image processing, and the image memory. and a host processor connected to the plurality of image processing units by a plurality of data transfer paths, and a host processor that transfers the unprocessed image data and the processed image data to the host processor individually for each image processing unit. and interface means for transferring data between the image processing units via the plurality of data transfer paths.

[Operation] According to the above configuration, image data resulting from parallel processing by a plurality of image processing units is transferred to a host processor via a plurality of data transfer paths.

[Examples] Examples according to the present invention will be described in detail below with reference to the accompanying drawings.

<Overall configuration> Figure 1 is an overall block diagram of the image processing device of the embodiment.
is a host processor, 2-4 to 2-8 are processing units (PUs) that perform parallel image processing, 3 is a communication path for inter-processor communication, 4 is a memory that stores programs etc. of the host processor 1, and 5 is image data 6 is a display controller for displaying the image memory, 7 is a CRT, 8 is a system bus, and 9 is a display bus.

The FIG. 1 system has two major functions.

One of them is that the host processor 1 has multiple communication paths. In the example of FIG. 1, host processor 1
has three communication paths 3-1+3-3.3-s. The second feature is that parallel processing and pipeline processing can be used selectively.

FIG. 5 shows the internal configuration of a microprocessor LSI (large scale integrated circuit) used in these PUs and the host processor 1. This microprocessor is manufactured by INMO in the UK.
It is 07800 made by 3N.

In the figure, 301 is a 32-bit CPU, and 306 to 30
9 is a link (communication path) interface, 304 is a 4-byte local memory, 305 is an interface for expanded memory of the built-in memory 304, 302 is a part that controls system services such as interrupts, and 300 is a floating point arithmetic unit. be. The four link interfaces built into the LSI are connected to each P TJ as shown in Figure 1.
join between. Also, when using this LSI as host processor 1, connect the three link interfaces to P
tl 2-1. 2-,. Connect with 2-5.

Image processing is performed by each PU, PU2-. 1 to 2-8 are
Prior to data processing, a processing program describing image processing procedures is sent from the host processor to the communication channel 1. ．． 3-3+
3. Receive through , , , local despatch °1
Store in 04. The second embodiment of such a program will be described with reference to the binarization process and image rotation process shown in FIGS. 7 and 9, respectively. The programs stored in the local memory 304 are stored as shown in FIG. That is, the processing program in FIG. 7 or 9 corresponds to the processing program in FIG. 6. In the parallel processing device of this embodiment, in order to efficiently perform parallel processing or vibeline processing, various data are stored in the local memory 30 in addition to processing programs, as shown in FIG.
Store in 4. The source processor number in FIG. 6 indicates the number of the other party's processor that received the data. Further, the transmission source processor number is the number of the transmission destination to which the image processing result is to be sent. In the system shown in Figure 1, the processor number is 0'' for host processor 1, 1'' for PU2-,
"2°°..." is assigned to PU2-.

In the case of simple parallel processing, each 1. -" (The destination processor number stored in J is the processor number "0°" of post-processor 1. On the other hand, for example, in the case of vibe line processing, the processor number according to the algorithm is stored. .Also, the adjacent processor number means this PU
This is the processor number of the PU that is in charge of processing the 11th divided image that is adjacent to the divided image that is in charge of.

(Parallel processing) As parallel processing, let us consider, for example, the case where the fourth drawing image is binarized using a threshold matrix. The processing procedure is shown in Fig. 7. Each element of is compared with a pixel of the image data (step S1), and the size is determined (step S2) and binarized as white or black (step 53.S4).Step S5
Then, the binarization result is stored in the local memory 304.

, are executed for all pixels in the same block (step S7). In step S8, it is determined whether the block currently being processed is the final block to be processed by this PU. If it is the last block, step S12
The processed image data is transferred to the unit indicated by the destination processor number. In this case, the destination processor number is "0" of the host processor 1, as described above.

In step S8, if there are still blocks to be processed, the process advances to step S9, and the local memory 3
Cut out the next block from 04. In step S10, it is determined whether this extracted block is in a boundary area. This can be seen from the fact that the cut out blocks do not have a 4×4 size. If it is not in the boundary area, the process returns to step S1 and the steps from step 51 described above are repeated. If it is in the boundary area, step S11
Then, the adjacent processor number is determined, necessary pixel data is obtained from that PU, and the process returns to step S1.

The above steps are common to each PU, and therefore, the PUs that have completed processing transfer the processing data to the host processor 1 all at once via the link interface (communication path 3). The host processor 1 uses this communication path 3-1, m
The data on l, , 3-s is stored in its own local memory 30
4 and returns to the image memory 5 via the system bus 8. The memory 4 is connected to the host processor 1 via the memory interface 305, and serves as an external memory.

<Effects of parallel processing method> Thus, the binarization image processing is completed. In this case, image processing such as binarization is performed independently for each divided image (unit of image processing) (for each PU), so
As shown in the flowchart of FIG. 7, communication between the 20s occurs only slightly, and it can be said that the communication bottleneck is only the communication between the host processor and each 20. However, since there are a plurality of ink-face communication paths between the host processor 1 and each 20, there is no reduction in processing speed. That is, as the host processor 1, a processor that has multiple communication channels and can transfer data in parallel via them is used, and due to 'X', the image data can be transferred at high speed. Furthermore, host processor 1
The receiving and passing of data such as commands and status between each 20 units can be realized in parallel, increasing speed.

Now, in this embodiment, the case where there are three communication paths between the host processor 1 and each 20 has been described, but the host processor 1 has two or more communication paths 3 and can transfer data in parallel via these. It is also possible to use a processor.

Furthermore, in the embodiment shown in the first figure, each PU performs data transfer and processing at the same time, thereby realizing multiple vibe line processing.

Vibration Line Processing Method> The binarized image processing described above is suitable for parallel processing in a pure sense because the processing for each 20 pixels is substantially independent of each other. However, when the PU responsible for the pixel position before processing and the PU responsible for the pixel position after processing become different, such as when rotating an image, communication between PUs increases, so the host Simply increasing the number of communication channels between the processors 1 and 20 is not enough to deal with the problem. Therefore, if vibration line processing is possible such as image rotation, each PU is logically combined to form a vibration line configuration. In this case, the system configuration remains the same as in Figure 1, with P
The processing program, source processor number, destination processor number, etc. stored in the local memory 304 of U are stored in each page.
It will be unique among u.

Image rotation is expressed by the following equation. In other words, the readout coordinates are (
xR, yv),, If the writing coordinates are (X,, Y,), then x, = cosθ·Xw-3INθ-Y.

YR=SINθ·xw+cosθ·Yl.

FIG. 8 shows a system that implements this image rotation by performing vibration line processing using four PUs. That is, the host processor 1 determines that the coordinate after rotation=the write coordinate (Xw).

Y, ) are generated one after another and transferred to PtJll, and the coordinate 2 read coordinates (XR, YR) before rotation are received from the PU2-3. Based on this readout coordinate j714 (X R, Y R), the contents of the image memory 5 are read out and the bit values are written in the old coordinates (Xw, Yw).

To explain specifically, the host processor 1 is Pu2-i
Send c=coordinates X,,Y,. In PU-1, a=CO5
Calculate θ·Xw. This a and the coordinates (X,.

Y, ) to PLII2. In PU2-2, XR=
a-5INθ-Y is calculated. PU 2-2 sends this calculation result XR and (Xw, Y,) to PU 2-4.

PU2-4 calculates b=SINθ-Xw. PU2-
4 is XR, (X,, Y,) and b as P U 2-3
send to PtJ2-s calculates YR=b+CO5θ·Y. Thus, XR and YR are host processor 1
sent to.

Here, the source processor number and destination processor number are summarized as follows.

FIG. 9 shows the image processing procedure of each PU. It is assumed that each PU receives its program, processor number, etc. from the host processor 1 and stores it in the internal local memory 304 before this PU procedure is executed. Further, for convenience of explanation, the processing procedure in FIG. 9 is shown in a general format for each PU. In step S20, the source processor number is read from the local memory 304. In step 321,
It waits for data from the sending source PIJ (or host processor 1). When the data is received, in step S22, part of the image processing imposed on this PtJ (for example, in the case of PU2-1 in FIG. 8, a=CO5θ·XW) is executed. In step S23, the destination processor number is read. In step S24, it is checked whether the destination is capable of receiving data, and if so, the processing result data is transmitted in step S25.

In this manner, in the system shown in FIG. 8, the four PUs form a four-stage vibe line configuration, and the rotation of one pixel is realized as a whole.

Furthermore, since the processing sequence is defined by the source and destination processor numbers in the local memory, each PU can perform continuous processing, achieving high-speed image rotation processing.

<Modification> As described above, the host processor 1 sends the processing procedure and processor number to each PU to select parallel processing using screen division or parallel processing using vibrine processing. In this case, these processing steps are performed in advance for each P.
It is stored in U and the host processor 1 issues the instruction I.
It is also possible to make the selection based on the information.

Although the above embodiment has been described with reference to the case where there are four or six PUs, it is also possible to easily realize a case where there are two or more PU2. Further, it is not necessary to use all PUs for processing, and it is sufficient to logically concatenate as many as necessary.

Furthermore, although the PUs are connected in a grid pattern, other connection forms such as star or ring connections can be easily applied.

[Effects of the Invention] As explained above, according to the parallel image processing device of the present invention, even if a plurality of image processing units are used, communication between the host processor and each processing unit can be performed multiplexed, and processing efficiency does not decrease. .

[Brief explanation of the drawing]

Fig. 1 is an overall diagram of a parallel image processing device according to an embodiment, Figs. 2 and 3 are diagrams explaining the conventional technology, and Fig. 4 shows an example of image division used in the conventional technology 9 and this embodiment. 5 is a configuration diagram of the image processing LSI used in this embodiment, FIG. 6 is a configuration diagram of the local memory, FIGS. 7 and 9 are flowcharts showing the control procedure of the embodiment, FIG. 8 is a diagram illustrating the configuration of a PU for image rotation. In the figure, 1... host processor, 2-1 to 2-s...
- Processing unit (PU), 3,1. ~3-6
...Communication path, 4...Memory, 5...Image memory,
301...CPU, 304...Local memory, 3
06-309...Link interface (communication interface. Patent applicant Canon Co., Ltd. Figure 1 Figure 3 Figure 4 Figure 5 Figure 6

Claims (2)

[Claims] (1) An image memory that stores image data to be image processed, a plurality of image processing units that perform image processing, and is connected to the image memory and connected to the plurality of image processing units by a plurality of data transfer paths. for each image processing unit, the image data before processing and the image data after processing are transferred between the host processor and each image processing unit via the plurality of data transfer paths. 1. A parallel image processing device comprising: an interface means. (2) The parallel image processing apparatus according to claim 1, wherein the image processing unit is a divided image.