JPS63187622A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent channeling and to ensure desirable recovery of crystallinity, by implanting inert atoms into a substrate form an amorphous layer and etching away only the amorphous layer by means of an isotropic etching means. CONSTITUTION:Inert As ions 2 are implanted into a substrate 1, whereby an amorphous layer 3 is formed from the surface to the inside of the substrate 1. Si<+> ions are implanted at an acceleration energy of 120 KeV and a dosage of 3.5 X 10<12>/cm<3> to form an Si implanted operation layer 4. Then, a process for etching the amorphous layer 3 precedes heat treatment of the implanted dopant atoms. In order to anneal the implanted active dopant atoms, the substrate 1 having the operation layer 4 is held at 850 deg.C for 15 minutes within the atmosphere of argon containing a small amount of arsine. Thereby, the crystallinity is recovered, the Si is activated and a uniform N-type conductive layer 4' can be obtained. Thus, channeling is prevented and desirable recovery of crystallinity is ensured.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention provides a method for preventing channeling that occurs during ion implantation into a semiconductor single crystal substrate (hereinafter abbreviated as a semiconductor substrate). The present invention relates to an improvement in a method for manufacturing a semiconductor device that includes an effective ion implantation process through an amorphous layer and a heat treatment process for activating the implanted ions, and is particularly suitable for manufacturing FETs using GaAs semiconductor substrates.

(Prior Art) The ion implantation method, which introduces active impurities in a certain amount from the surface of a semiconductor substrate to a certain depth and has excellent uniformity, has become an indispensable method for semiconductor processes. However, when ions are implanted into a single crystal with a three-dimensional arrangement unique to crystals, the interaction between the incident ions and the target single crystal substrate increases by +11 depending on the direction of ion incidence.
On the other hand, it is well known that when ions are implanted from a low-index crystal axis direction, a so-called axial channeling phenomenon occurs, so that the range of implanted ions is significantly increased compared to when implanted from a random direction.

Even when ion implantation is shifted from this low-index crystal axis direction to prevent the occurrence of axial channeling, a so-called plane channeling phenomenon may occur depending on the direction of deviation of the ion beam incidence direction, and this also increases the range of the implanted ions. This makes it difficult to control.

To prevent this surface channeling, activate the impurity atoms into the semiconductor substrate prior to the ion beam.

An amorphous layer that disturbs the crystal orientation of a semiconductor substrate by irradiating it with an electrically inert particle beam (hereinafter this description will refer to ion, atomic, or molecular beams) A method is known in which desired active impurity atoms are implanted, followed by heat treatment to activate the impurity atoms.

When this method is applied, even if the beam incidence direction of the desired active impurity atoms coincides with the planar channeling direction, the incident ions are scattered by the disordered crystallinity and the planar channeling phenomenon does not occur.

(Problems to be Solved by the Invention) Such means require a heat treatment (annealing) step to activate N impurity atoms while leaving damage introduced when forming an amorphous layer on a semiconductor substrate. Therefore, if the implantation dose (m) of the inactive impurity is large, the amount of damage will be too large and the activation of the implanted impurity will be insufficient at the normal annealing temperature. As a result, the desired impurity concentration distribution in the active layer has the expected value of 1! ) is inevitable.

An object of the present invention is to provide a novel method for manufacturing a semiconductor device 1r1 that eliminates the above-mentioned difficulties.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, in one method of the present invention, a semiconductor substrate is irradiated with a beam of electrically inert atoms to form an amorphous layer, and then the amorphous layer is formed on a semiconductor substrate. After implanting the desired active impurity atoms through the crystalline layer, the amorphous layer is dissolved away by isotropic etching means.

Furthermore, a method is adopted in which a heat treatment process is performed to activate the implanted active impurity atoms.

(Function) In the method for manufacturing a semiconductor device according to the present invention, an amorphous layer formed by irradiating a semiconductor substrate with a beam of an electrically inactive element can be easily dissolved by isotropic etching means. This method was completed based on the fact that a mirror surface is formed on the semiconductor substrate after this isotropic etching process.

By the way, gallium arsenide is suitable for the semiconductor substrate to which the present invention is applied, and the anisotropic etching process, which is known as a general etching method, i.e., dry process, cannot be used because it may damage the semiconductor substrate. For the isotropic etching solution, a mixed solution prepared by adding hydrogen peroxide to one selected from the group consisting of hydrochloric acid, phosphoric acid, and caustic soda-ammonium water can be used. Examples of impurity elements that are electrically inactive with respect to the semiconductor substrate include gallium, arsenic,
Glypton, Cannon, and argon are preferable, and the conditions for forming the amorphous layer are Be1 of 50 KeV to 100 KeV.
1 and its concentration is s x to”/ad to 5X
1014/d, and the thickness of the amorphous layer is 100 to 500.

As active impurity atoms to be ion-implanted through this amorphous layer, Si ions are ion-implanted at 50 KeV to 150 KeV and 0.1
It is formed to a thickness of ~0.2 μs.

Furthermore, as mentioned above, after the amorphous layer was removed by isotropic etching, the ion-implanted active impurity atoms were annealed. More than double N5 = 2.3X101
2/cJ was obtained. This is presumed to be because the amorphous layer is removed by isotropic etching prior to the heat treatment step, and crystallinity is smoothly recovered during the subsequent heat treatment.

Furthermore, since there is a large difference in etching speed between the amorphous layer and the semiconductor substrate, it is easy to dissolve only this amorphous layer, and no deterioration in the uniformity or reproducibility of the ion-implanted layer occurs. Please note that this has also been confirmed.

(Example) An example of the present invention will be described in detail with reference to FIG. 1 a = d and FIGS. 2 a and b.

An example of implanting donor impurity ions into a gallium arsenide semiconductor substrate, which has superior high frequency characteristics compared to a silicon semiconductor element, will be described.

A semi-insulating GaAs substrate 1 with a (100) plane orientation is prepared,
On the other hand, electrically inactive As ions 2 are implanted at an acceleration energy of 50 KeV and a dose of 2 XIO''/at?.

(Fig. 1a) During this ion implantation process, the normal (<100) direction of the semiconductor substrate 1 is supported at an angle of 7 degrees with respect to the direction of incidence of the ion beam in order to avoid axial channeling. Within this tilted plane, the orientation can be freely set without any particular designation.

The As ions implanted into the GaAs substrate through this step are distributed within the GaAs substrate 1 approximately as shown by the curve 5 shown in FIG. 2a. As a result, an amorphous layer 3 (FIG. 2b) is formed from the surface of the GaAs semiconductor substrate 1 inward, and the average projected range of implanted As is Rp(As), and its standard deviation is ΔRp(As). ), most of it is Rp(As)+Δ
It exists from near Rρ(As) to the surface of the GaAs substrate. (Fig. 2b) Note that under these implantation conditions, Rp is 214
A, ΔRpα There are 109 people, so Δnp + +'+p
There were 323 people. With this amorphous layer 3 formed, Si+13 (indicated as 4 in the figure) is accelerated at an energy of 120 KeV and a dose of ff3.5 as shown in the first +qb.
x 7 with respect to the direction of incidence of the ion beam as shown in
This GaAs semiconducting substrate can be freely installed within the inclined plane, and if the incident direction of the Si ion beam is
1, 10) Even if the plane directions match, the incident SL ions are scattered (dechanneled) due to this disordered crystallinity and are implanted without causing plane channeling. The thickness of the amorphous layer 3 is 100 to 500, and the injection operation λ is 0.1.
μm to 0.2βm.

The element λ·mi used to form the amorphous layer 3 is Ga.
Gallium, krypton, cannon, and argon, which are electrically inert to As semiconductor-jAF2, can be applied, and the implantation conditions are acceleration and pressure of 50 KeV to 1 O.
OKev dose is 5X 101)/ffl to 5X
10"/d.

Next, the process moves on to the step of dissolving the amorphous layer 3, which precedes the aging of the implanted active impurity atoms. (FIG. 1C) As described above, the Dry Procedure, which is estimated to cause 411 scratches on the GaAs semiconductor substrate, is excluded and 1 isotropic etching step is used.

As for the etching solution, as described in 1) η, a mixed solution consisting of hydrochloric acid, one selected from the group consisting of caustic soda, phosphoric acid, and aqueous ammonia and hydrogen peroxide can be used; This method is particularly suitable because only the amorphous layer formed on the GaAs semiconductor substrate can be dissolved and a mirror surface can be obtained.

Concentrated hydrochloric acid is used as the hydrochloric acid, and boiling in this solution easily dissolves only the amorphous layer, and when the so-called immersion method is adopted, the time required is more than 10 times, which is unfavorable in terms of production efficiency. .

The composition of the mixed solution of phosphoric acid and hydrogen peroxide solution was 3:H,0,1:112050 by volume, and the etching speed was 500 people and 7 minutes at 15°C.

If the volume ratio of caustic soda and hydrogen peroxide solution is 1=1, the etching rate is 2500 people/min at room temperature, Na0t12:H
At 2O,1 (volume ratio), it is 15008/min. In any case, these isotropic etching solutions simplify the amorphous X etching process and do not do anything to the continuous GaAs semiconductor substrate. The feature of hydrochloric acid is that it can be removed without making any noise, and the key point of hydrochloric acid is that it can form a mirror surface after etching.

Next, as an annealing step for the implanted active impurity atoms, the GaAs semiconductor substrate 1 having the Si implanted active layer 4 is held at 850° C. for 15 minutes in an argon atmosphere containing a small amount of arsine (AsHi) to crystallize it. A uniform n-type conductive layer 4' is formed by recovering the properties and activating Si.
complete. (FIG. 1d) Furthermore, if an FET is formed using this method using a GaAs semiconductor substrate in a conventional manner, its characteristics will be improved.

〔Effect of the invention〕

As described above, in the present invention, an amorphous layer is formed by implanting electrically inactive atoms into a semiconductor substrate, and then necessary active impurity atoms are implanted to prevent channeling.Furthermore,
By dissolving only this amorphous layer using an isotropic etching method, heat treatment is performed while excluding damage that occurs during implantation. The recovery was also good, and the active impurity N
s is significantly increased compared to the conventional case.

[Brief explanation of the drawing]

Fig. 1 a = d is a sectional view explaining the present invention in detail, Fig. 2 a is a cross-sectional view showing the details of the present invention;
2 is a curve diagram showing the relationship between the depth from the surface of the semiconductor substrate and the sound of rain, and No. 2 [4b] is a cross-sectional view of the semiconductor substrate after the method of the present invention has been applied. 1..GaAs semiconductor 1. ! ; Handling 2... As ion beam \3... Amorphous layer 4... S1 ion beam 11 and SL implantation operation layer 4'...
・N conductive layer agent Patent attorney Inoue - Male Figure 1 Figure 2

Claims (1)

[Claims] Active impurity atoms are implanted into the semiconductor substrate through an amorphous layer formed by irradiating the semiconductor substrate with a beam of an electrically inert element, and this amorphous layer is etched by isotropic etching. A method for manufacturing a semiconductor device, which comprises performing heat treatment to activate the implanted impurity atoms after dissolution.