JPS63187482U - - Google Patents

Info

Publication number
JPS63187482U
JPS63187482U JP7965687U JP7965687U JPS63187482U JP S63187482 U JPS63187482 U JP S63187482U JP 7965687 U JP7965687 U JP 7965687U JP 7965687 U JP7965687 U JP 7965687U JP S63187482 U JPS63187482 U JP S63187482U
Authority
JP
Japan
Prior art keywords
control signal
stereo
demodulation circuit
lcd
tuned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7965687U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7965687U priority Critical patent/JPS63187482U/ja
Publication of JPS63187482U publication Critical patent/JPS63187482U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Television Receiver Circuits (AREA)
JP7965687U 1987-05-26 1987-05-26 Pending JPS63187482U (enrdf_load_stackoverflow)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7965687U JPS63187482U (enrdf_load_stackoverflow) 1987-05-26 1987-05-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7965687U JPS63187482U (enrdf_load_stackoverflow) 1987-05-26 1987-05-26

Publications (1)

Publication Number Publication Date
JPS63187482U true JPS63187482U (enrdf_load_stackoverflow) 1988-11-30

Family

ID=30929725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7965687U Pending JPS63187482U (enrdf_load_stackoverflow) 1987-05-26 1987-05-26

Country Status (1)

Country Link
JP (1) JPS63187482U (enrdf_load_stackoverflow)

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