JPS6318741A - Bus interface circuit - Google Patents

Bus interface circuit

Info

Publication number
JPS6318741A
JPS6318741A JP16270186A JP16270186A JPS6318741A JP S6318741 A JPS6318741 A JP S6318741A JP 16270186 A JP16270186 A JP 16270186A JP 16270186 A JP16270186 A JP 16270186A JP S6318741 A JPS6318741 A JP S6318741A
Authority
JP
Japan
Prior art keywords
signal
driver
section
control section
communication terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16270186A
Other versions
JPH0771086B2 (en
Inventor
Kimiyo Iwamoto
Michiaki Okano
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61162701A priority Critical patent/JPH0771086B2/en
Publication of JPS6318741A publication Critical patent/JPS6318741A/en
Publication of JPH0771086B2 publication Critical patent/JPH0771086B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Lifetime legal-status Critical

Links

Abstract

PURPOSE: To automatically restore the titled circuit into the normal state so long as no recovery disable fault takes place in an internal circuit component in a communication terminal equipment by applying initializing to a signal control means generating signal information forcibly if a fault is detected at the access of a common signal channel.
CONSTITUTION: An output Q of a flip-flop 3e is fed to a driver 5 as a driver enable (ENB)/disable (DTS) signal. With the said signal at L level, the driver 5 sends a signal from a coding section 4 to a transmission line T while driving a transmission transformer 6 and with the signal at H level, the driver 5 disconnects the communication terminal equipment from the transmission line by bringing the sent output into a high impedance state. Since a supervisory section 3 supplies a reset signal to a control section 1 in this case, the section 3 initializes a microprocessor 1a, a data link controller 1d and circuit components in the control section. Thus, even if malfunction of the microprocessor 1a takes place due to noise, the control section is restored to the initial state automatically.
COPYRIGHT: (C)1988,JPO&Japio
JP61162701A 1986-07-10 1986-07-10 Basuinta - Fueisu circuit Expired - Lifetime JPH0771086B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61162701A JPH0771086B2 (en) 1986-07-10 1986-07-10 Basuinta - Fueisu circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61162701A JPH0771086B2 (en) 1986-07-10 1986-07-10 Basuinta - Fueisu circuit

Publications (2)

Publication Number Publication Date
JPS6318741A true JPS6318741A (en) 1988-01-26
JPH0771086B2 JPH0771086B2 (en) 1995-07-31

Family

ID=15759658

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61162701A Expired - Lifetime JPH0771086B2 (en) 1986-07-10 1986-07-10 Basuinta - Fueisu circuit

Country Status (1)

Country Link
JP (1) JPH0771086B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6446343A (en) * 1987-08-13 1989-02-20 Fujitsu Ten Ltd Fail safe circuit
JPH01303942A (en) * 1988-06-01 1989-12-07 Hitachi Ltd Communication control system
US6088908A (en) * 1997-09-19 2000-07-18 Fujitsu Limited Method of making a head slider
US8902760B2 (en) 1998-04-10 2014-12-02 Chrimar Systems, Inc. Network system and optional tethers

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5494845A (en) * 1978-01-11 1979-07-26 Hitachi Ltd Bus control unit for data delivery unit
JPS60128741A (en) * 1983-12-16 1985-07-09 Mitsubishi Electric Corp Recovery processing device of computer system
JPS62136144A (en) * 1985-12-10 1987-06-19 Matsushita Electric Ind Co Ltd Home bus line acquisition and supervising system
JPS62203441A (en) * 1986-03-03 1987-09-08 Hitachi Ltd Abnormality processing circuit for repeater

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5494845A (en) * 1978-01-11 1979-07-26 Hitachi Ltd Bus control unit for data delivery unit
JPS60128741A (en) * 1983-12-16 1985-07-09 Mitsubishi Electric Corp Recovery processing device of computer system
JPS62136144A (en) * 1985-12-10 1987-06-19 Matsushita Electric Ind Co Ltd Home bus line acquisition and supervising system
JPS62203441A (en) * 1986-03-03 1987-09-08 Hitachi Ltd Abnormality processing circuit for repeater

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6446343A (en) * 1987-08-13 1989-02-20 Fujitsu Ten Ltd Fail safe circuit
JPH01303942A (en) * 1988-06-01 1989-12-07 Hitachi Ltd Communication control system
JP2528938B2 (en) * 1988-06-01 1996-08-28 株式会社日立製作所 Communication control system
US6088908A (en) * 1997-09-19 2000-07-18 Fujitsu Limited Method of making a head slider
US8902760B2 (en) 1998-04-10 2014-12-02 Chrimar Systems, Inc. Network system and optional tethers
US8942107B2 (en) 1998-04-10 2015-01-27 Chrimar Systems, Inc. Piece of ethernet terminal equipment
US9019838B2 (en) 1998-04-10 2015-04-28 Chrimar Systems, Inc. Central piece of network equipment
US9049019B2 (en) 1998-04-10 2015-06-02 Chrimar Systems, Inc. Network equipment and optional tether
US9812825B2 (en) 1998-04-10 2017-11-07 Chrimar Systems, Inc. Ethernet device

Also Published As

Publication number Publication date
JPH0771086B2 (en) 1995-07-31

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