JPS63186457A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS63186457A
JPS63186457A JP62017170A JP1717087A JPS63186457A JP S63186457 A JPS63186457 A JP S63186457A JP 62017170 A JP62017170 A JP 62017170A JP 1717087 A JP1717087 A JP 1717087A JP S63186457 A JPS63186457 A JP S63186457A
Authority
JP
Japan
Prior art keywords
substrates
wiring
integrated circuit
surface
rear
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62017170A
Inventor
Kenichi Mizuishi
Takao Mori
Akimasa Onozato
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62017170A priority Critical patent/JPS63186457A/en
Publication of JPS63186457A publication Critical patent/JPS63186457A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE: To obtain a lamination-type semiconductor device wherein the area of an integrated circuit substrate occupied by a wiring region can be reduced, the total module can be miniaturized, and the high speed quality can be improved, by laminating a plurality of semiconductor integrated circuit substrates having a three-dimensional structure wherein wiring patterns for electric connection are formed on the surface, the rear, and the side surface.
CONSTITUTION: A semiconductor integrated circuit substrate 10 has a three dimensional structure wherein wiring patterns 13 for electric connection are formed on the surface, the rear and the side surface. A plurality of the substrates are laminated, and wiring connection between each of the substrates 10 is made via the above-mentioned wiring patterns 13. For example, a computer module is constituted by stacking the integrated circuit substrates 10 of wafer scale. The central part of the substrate 10 is assigned to an active element region 11 constituted of memories and logic gates. These integrat ed circuit substrates 10 are stacked in 10W200 stages to realize a computer system. The wiring connection between the substrates 10 is made by mutually connecting the wiring layers 13 formed on the surface, the side surface, and the rear via soldering electrodes 14. Supporting bodies 15 are inserted between the substrates in order to prevent the deformation of the soldering electrodes 14.
COPYRIGHT: (C)1988,JPO&Japio
JP62017170A 1987-01-29 1987-01-29 Semiconductor device and its manufacture Pending JPS63186457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62017170A JPS63186457A (en) 1987-01-29 1987-01-29 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62017170A JPS63186457A (en) 1987-01-29 1987-01-29 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS63186457A true JPS63186457A (en) 1988-08-02

Family

ID=11936480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62017170A Pending JPS63186457A (en) 1987-01-29 1987-01-29 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS63186457A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5426566A (en) * 1991-09-30 1995-06-20 International Business Machines Corporation Multichip integrated circuit packages and systems
US5502667A (en) * 1993-09-13 1996-03-26 International Business Machines Corporation Integrated multichip memory module structure
US5517754A (en) * 1994-06-02 1996-05-21 International Business Machines Corporation Fabrication processes for monolithic electronic modules
US5561622A (en) * 1993-09-13 1996-10-01 International Business Machines Corporation Integrated memory cube structure
US5616962A (en) * 1992-01-24 1997-04-01 Kabushiki Kaisha Toshiba Semiconductor integrated circuit devices having particular terminal geometry
WO2000038234A1 (en) * 1998-12-04 2000-06-29 Thin Film Electronics Asa Scalable data processing apparatus

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5426566A (en) * 1991-09-30 1995-06-20 International Business Machines Corporation Multichip integrated circuit packages and systems
US5616962A (en) * 1992-01-24 1997-04-01 Kabushiki Kaisha Toshiba Semiconductor integrated circuit devices having particular terminal geometry
US5773321A (en) * 1992-01-24 1998-06-30 Kabushiki Kaisha Toshiba Semiconductor integrated circuit devices having particular terminal geometry and mounting method
US5502667A (en) * 1993-09-13 1996-03-26 International Business Machines Corporation Integrated multichip memory module structure
US5561622A (en) * 1993-09-13 1996-10-01 International Business Machines Corporation Integrated memory cube structure
US5517754A (en) * 1994-06-02 1996-05-21 International Business Machines Corporation Fabrication processes for monolithic electronic modules
WO2000038234A1 (en) * 1998-12-04 2000-06-29 Thin Film Electronics Asa Scalable data processing apparatus

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