JPS63179548A - Wiring structure of semiconductor integrated circuit device - Google Patents
Wiring structure of semiconductor integrated circuit deviceInfo
- Publication number
- JPS63179548A JPS63179548A JP1281787A JP1281787A JPS63179548A JP S63179548 A JPS63179548 A JP S63179548A JP 1281787 A JP1281787 A JP 1281787A JP 1281787 A JP1281787 A JP 1281787A JP S63179548 A JPS63179548 A JP S63179548A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- wiring
- film
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 230000007423 decrease Effects 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 238000009413 insulation Methods 0.000 description 7
- 239000012528 membrane Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
こ・の発明は、半導体集積回路装置に関し、特に配線構
造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention relates to a semiconductor integrated circuit device, and particularly to a wiring structure.
第２図（ａ）、 （ｂ）は従来の半導体集積回路装置に
おける配線構造を示す断面図であって、第２図（ａ）は
一層配線構造を示し、第２図（ｂ）は二層構造を示す。FIGS. 2(a) and 2(b) are cross-sectional views showing wiring structures in conventional semiconductor integrated circuit devices, with FIG. 2(a) showing a single-layer wiring structure and FIG. 2(b) showing a two-layer wiring structure. Show the structure.
同図において、１は基板、２は基板１の表面に形成され
た絶縁膜、３ａ〜３Ｃは絶縁膜２の上に形成された配線
膜である。そして、この配線膜３ａ〜３Ｃは、ＣＶ Ｄ
（Ｃｈｅ＋＋＋１ｃａｌ Ｖａｐｅｒ Ｄｅｐｏｓｉ
ｔｉｏｎ）法またはＰ Ｖ Ｄ （Ｐｈｙｓｉｃａｌ
Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法等により導電膜
を形成した後、写真製版技術とエツチング法を利用して
、選択的にパターンニングを行った状態を示す。４は絶
縁膜であって、第２図（ａ）ではパッシベーション膜、
第２図（ロ）では相関絶縁膜となる。また、第２図（ｂ
）における６は二層目の配線膜である。In the figure, 1 is a substrate, 2 is an insulating film formed on the surface of the substrate 1, and 3a to 3C are wiring films formed on the insulating film 2. The wiring films 3a to 3C are CV D
(Che+++1cal Vaper Deposit
tion) method or P V D (Physical
This figure shows a state where a conductive film is formed by a vapor deposition method or the like, and then selectively patterned using a photolithography technique and an etching method. 4 is an insulating film, which in FIG. 2(a) is a passivation film;
In FIG. 2(b), it becomes a correlated insulating film. In addition, Fig. 2 (b
6 in ) is the second layer wiring film.
このように構成された半導体集積回路装置においては、
パターンニングされた配線膜３および６は絶縁膜２およ
び４によって互いに絶縁されており、特に第２図（ａ）
における絶縁膜４は表面保護の目的も兼ねている。特に
、多層配線構造とする場合に、第３図に示すように眉間
絶縁膜４の平坦性が悪いと、その段差部Ａにおける配線
膜６の被着率が悪化して断線等が生ずることから、この
部分における配線膜の信頼性が大幅に低下する。このた
めに、多層配線構造においては第２図（ｂ）に示したよ
うに、絶縁膜の平坦化が行われている。In the semiconductor integrated circuit device configured in this way,
The patterned wiring films 3 and 6 are insulated from each other by the insulating films 2 and 4, especially as shown in FIG. 2(a).
The insulating film 4 also serves the purpose of surface protection. In particular, in the case of a multilayer wiring structure, if the flatness of the glabellar insulating film 4 is poor as shown in FIG. , the reliability of the wiring film in this portion is significantly reduced. For this reason, in a multilayer wiring structure, the insulating film is planarized as shown in FIG. 2(b).
従来の半導体集積回路装置における配線構造は以上のよ
うに構成されているので、配線間隔の減少に伴って、ま
た多層配線構造をとるために眉間絶縁膜の表面を平坦化
することによる配線膜の直上に位置する絶縁膜の膜圧減
少に伴って、配線膜間の容量が増大することから、配線
間における電気信号の混信（クロストーク）および容量
抵抗（Ｃ−Ｒ）結合による電気信号の伝達遅延が生じて
しまう。また、絶縁膜が有する応力に起因して配線に断
線が生ずる等の種々問題点があった。The wiring structure in conventional semiconductor integrated circuit devices is configured as described above, so as the wiring spacing decreases and the surface of the glabella insulating film is flattened to obtain a multilayer wiring structure, the wiring film becomes thinner. As the film thickness of the insulating film located directly above decreases, the capacitance between wiring films increases, resulting in electrical signal interference (crosstalk) between wirings and electrical signal transmission due to capacitance-resistance (C-R) coupling. This will cause a delay. Furthermore, there have been various problems such as disconnection of wiring due to the stress of the insulating film.
この発明は以上のような問題点を解消するためになされ
たものであって、配線間容量および絶縁膜の応力を低減
することによって、電気信号の混信および伝達遅延を少
なくするとともに、断線が生じない信頼性の高い配線構
造を得ることを目的とするものである。This invention was made to solve the above-mentioned problems, and by reducing the capacitance between wirings and the stress of the insulating film, it reduces electrical signal interference and transmission delay, and also reduces the possibility of wire breakage. The purpose of this is to obtain a highly reliable wiring structure.
この発明に係る半導体集積回路装置の配線構造は、配線
股間の電気的絶縁を絶縁膜に空洞を加えて行うものであ
る。In the wiring structure of a semiconductor integrated circuit device according to the present invention, electrical insulation between wiring legs is achieved by adding a cavity to an insulating film.
この発明における半導体集積回路装置の配線構造は、配
線膜間の絶縁を絶縁膜に加えて空洞で行うものであるこ
とから、配線間容量を下げると共に、空洞を形成するこ
とによって絶縁膜が保有する応力が低下するために、配
線膜の断線が防止されることになる。In the wiring structure of the semiconductor integrated circuit device according to the present invention, insulation between wiring films is provided by a cavity in addition to an insulating film. Therefore, the capacitance between wirings is reduced, and by forming the cavity, the insulation film retains its properties. Since the stress is reduced, disconnection of the wiring film is prevented.
以下、この発明の一実施例を図について説明する。第１
図（ａ）において、５．ａ、５ｂは配線膜３ａ〜３０間
に位置する絶縁膜４中に、絶縁性の一向上と絶縁膜４が
保有する応力を取り除くために形成された略配線膜の厚
みと同等の高さを有する空洞であって、この空洞５の底
部は基板１０表面に形成されている絶縁膜２に接してい
る。An embodiment of the present invention will be described below with reference to the drawings. 1st
In figure (a), 5. a and 5b have a height approximately equal to the thickness of the wiring film formed in the insulating film 4 located between the wiring films 3a to 30 in order to improve the insulation properties and remove the stress possessed by the insulating film 4. The bottom of the cavity 5 is in contact with the insulating film 2 formed on the surface of the substrate 10.
第１図（ロ）は多層構造に適用したものであって、導電
膜３と二層目の配線膜６との間に位置する絶縁膜４の内
部に、略配線膜３の幅に一致する空洞５を設けて、配線
膜３，６間の絶縁性向上と絶縁膜４が保有する応力を除
去するものである。FIG. 1(b) shows a structure applied to a multilayer structure, in which a portion of the insulating film 4 located between the conductive film 3 and the second-layer wiring film 6 is formed so that the width of the wiring film 3 approximately corresponds to the width of the wiring film 3. The cavity 5 is provided to improve insulation between the wiring films 3 and 6 and to remove stress held by the insulating film 4.
第１図（Ｃ）は第１図（ａ）における空洞５ａ、５ｂの
底部を絶縁膜２に接しさせたのに対し、この底部を絶縁
膜２から浮かしたものである。In FIG. 1(C), the bottoms of the cavities 5a and 5b in FIG. 1(a) are in contact with the insulating film 2, whereas these bottoms are lifted from the insulating film 2.
第１図（司は配線膜３ａ〜３０間に位置する絶縁膜４を
全て除去することによって、該部分を全て空洞５ａ〜５
ｄとしたものである。In FIG. 1, by removing all the insulating film 4 located between the wiring films 3a to 30, all the cavities 5a to 5 are removed.
d.
第１図（ｅ）は多層構造に適用したものであって、導電
膜３と二層目の配線膜６との間に位置する絶縁膜４を全
て除去して、この部分を全て空洞５としたものである。FIG. 1(e) shows a case applied to a multilayer structure, in which all of the insulating film 4 located between the conductive film 3 and the second wiring film 6 is removed, and this part is completely converted into a cavity 5. This is what I did.
６ａ、６ｂは二層目の配線膜を示す。6a and 6b indicate the second layer wiring film.
第１図（ｆ）は配線膜３ａ、３ｂの周囲に位置する絶縁
膜４の内部に、配線膜３ａ、３ｂを取り囲むように空洞
５を設けることによって、絶縁膜４を絶縁膜４ａと絶縁
膜４ｂに分割して二重構造としたものである。FIG. 1(f) shows that a cavity 5 is provided inside the insulating film 4 located around the wiring films 3a and 3b so as to surround the wiring films 3a and 3b, so that the insulating film 4 can be separated from the insulating film 4a and the insulating film. It is divided into 4b to form a double structure.
第１図（樽は配線膜３ａ〜３０間に位置する絶縁膜４ａ
の内部に、配線膜３ａ、３ｃの側面のみに接する空洞５
ａ、５ｂを設けたものであって、配線膜３ａ〜３０間の
絶縁Ｍ２に接する部分には、絶縁膜４ｂ、４ｃが残され
ている。FIG. 1 (The barrel is an insulating film 4a located between wiring films 3a to 30.
There is a cavity 5 in contact with only the side surfaces of the wiring films 3a and 3c.
a, 5b are provided, and insulating films 4b, 4c are left in the portions contacting insulation M2 between wiring films 3a to 30.
半導体集積回路装置における配線間の静電容量は、配線
形状および配線間隔等にも依存するが、基本的には絶縁
膜材料が有する誘電率に大きく左右される。そして、半
導体集積回路装置は微細化と共に配線ピッチが狭くなり
、かつ配線自由度を向上させるために多層化が進んでい
る。ここで、多層配線構造においては、下地絶縁膜の平
坦性が配線の信頼性およびパターンニング性の向上に大
きく寄与する。The capacitance between wires in a semiconductor integrated circuit device depends on the shape of the wires, the distance between the wires, and the like, but basically it is greatly influenced by the dielectric constant of the insulating film material. As semiconductor integrated circuit devices become smaller, the wiring pitch becomes narrower, and multilayering is progressing in order to improve the degree of freedom in wiring. Here, in a multilayer wiring structure, the flatness of the underlying insulating film greatly contributes to improving the reliability and patterning properties of the wiring.
しかしながら、平坦化と共に配線のような凸部上の絶縁
膜はその膜圧が薄くなる傾向に進む。また、配線間容量
は配線数および層数の増加と共に複雑なマトリックスで
表されることになるが、基本的には平行平板近似のＣ＝
εε。Ｓ／ｌを拡張したものとなる。従って、容量を減
らすためには、配線の表面積Ｓを下げること、絶縁膜の
膜厚ｔを厚くすること、絶縁膜の比誘電率ε（ε。は真
空中の誘電率）を小さくすれば良いことになる。However, as planarization progresses, the film thickness of the insulating film on convex portions such as wiring tends to become thinner. In addition, as the number of wires and layers increases, the inter-wire capacitance will be represented by a complex matrix, but basically the parallel plate approximation C=
εε. It is an extension of S/l. Therefore, in order to reduce the capacitance, it is necessary to lower the surface area S of the wiring, increase the film thickness t of the insulating film, and reduce the dielectric constant ε (ε. is the dielectric constant in vacuum) of the insulating film. It turns out.
ここで、表面積Ｓは配線抵抗、電流容量および信幀性上
から下限があり、また絶縁膜の膜厚しは先に述べたよう
に、平坦化およびコンタクトホールを形成する場合の加
工性上から、あまり厚くすることは出来ない。従って、
絶縁膜の比誘電率εを下げる方法が最後に残るが、従来
広く使用されているＳｔ Ｏ，の比誘電率εは３．５〜
４であり、Ｓ＋ｚＮ４の比誘電率εは７〜１０であり、
Ａ ｌ ２０、の比誘電率εは７〜９である。なお、ポ
リイミド系樹脂では比誘電率εが３以下のものもあるが
、比誘電率εが１のものは存在しない。Here, the surface area S has a lower limit from the viewpoint of wiring resistance, current capacity, and reliability, and the thickness of the insulating film is determined from the viewpoint of processability when flattening and forming contact holes, as mentioned earlier. , it cannot be made too thick. Therefore,
The last method left is to lower the dielectric constant ε of the insulating film, and the dielectric constant ε of St O, which has been widely used in the past, is 3.5 to 3.5.
4, and the relative dielectric constant ε of S+zN4 is 7 to 10,
The dielectric constant ε of Al 20 is 7 to 9. Note that although some polyimide resins have a dielectric constant ε of 3 or less, there are no polyimide resins with a dielectric constant ε of 1.
一方、ガスの場合には、−気圧以下ではＡｒ 。On the other hand, in the case of gas, it is Ar below -atmospheric pressure.
Ｏｚ 、Ｈｚ 、 Ｎ！ 、 Ｃｏｔ 、 Ｈｅの比誘
電率εがほとんど１であり、減圧状態になればますます
１に近くなる。Oz, Hz, N! , Cot, and He have a relative dielectric constant ε of almost 1, which becomes closer to 1 as the pressure is reduced.
半導体集積回路装置の製造工程において、絶縁膜の形成
プロセスでは、条件を制御すれば空洞の形成と膜の堆積
を自由に行うことが出来る。一般に良く用いられるＣＶ
Ｄ法やスパッタリング法では、減圧下での処理プロセス
であるために、形成された空洞中には、プロセスガスや
その分解生成ガスが含まれるが、これは減圧状態である
。従って、平行平板近似で電極間が絶縁膜−空洞−絶縁
膜の場合、
１ ／ Ｃ＝ ２ ／ ＣＩ＋ １ ／ Ｃｚ（但し
、ＣＩは絶縁膜による容量、Ｃｔは空洞による容Ｉ）と
なり、これらを整理すると、Ｃ＝Ｃ，・Ｃｔ ／ （２
Ｃｒ ＋Ｃｔ ）となる。この結果、空洞の形成により
、絶縁層のみの場合に較べて、配線間の容量が下がり、
信号の混信や信号の伝送遅延が大幅に改善される。また
、絶縁膜には形成条件にも影響するが、かなりの応力が
存在する。特に配線膜がアルミ合金から成る場合には、
絶縁膜の応力が原因となって、配線膜の一部が欠損した
り、著しい場合には断線となってしまう。これに対して
、空洞部よ配線膜が保有する応力を緩和する効果を示し
、配線の信頼性向上にも寄与する。In the manufacturing process of a semiconductor integrated circuit device, in the process of forming an insulating film, the formation of a cavity and the deposition of a film can be freely performed by controlling the conditions. Commonly used CV
In the D method and the sputtering method, since the process is performed under reduced pressure, the formed cavity contains the process gas and its decomposed gas, but this is under reduced pressure. Therefore, when the electrodes are insulating film-cavity-insulating film in the parallel plate approximation, 1 / C = 2 / CI + 1 / Cz (where CI is the capacitance due to the insulating film and Ct is the capacitance I due to the cavity), and these can be expressed as To summarize, C=C,・Ct/(2
Cr + Ct). As a result, due to the formation of cavities, the capacitance between wirings decreases compared to the case of only an insulating layer.
Signal interference and signal transmission delay are significantly improved. In addition, considerable stress exists in the insulating film, although this also affects the formation conditions. Especially when the wiring film is made of aluminum alloy,
Due to the stress in the insulating film, a portion of the wiring film may be damaged, or in severe cases, the wire may be disconnected. On the other hand, it exhibits the effect of alleviating the stress possessed by the cavity and the wiring film, and also contributes to improving the reliability of the wiring.
なお、上記実施例においては、配線間についてのみ説明
したが、不純物拡散層間および不純物拡散層と配線間の
場合にも適用しても良いことば言うまでもない。また、
導体としては、多結晶シリコン、金属、不純物拡散層の
いずれか又はこれらの積層構造の使用が可能である。更
に、絶縁膜としては、シリコン酸化膜、シリコン窒化膜
、シリコンオキシナイトライド膜、金属酸化膜、有機絶
縁膜等の使用が可能である。In the above embodiment, only the case between wirings has been described, but it goes without saying that the invention may also be applied to cases between impurity diffusion layers and between an impurity diffusion layer and wirings. Also,
As the conductor, polycrystalline silicon, a metal, an impurity diffusion layer, or a laminated structure of these can be used. Further, as the insulating film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a metal oxide film, an organic insulating film, etc. can be used.
以上説明したように、この発明による半導体集積回路装
置の配線構造によれば、絶縁膜中に空洞部分を形成した
ものであるために、導体層間の容量低下と絶縁膜が保有
する応力の緩和が可能になり、これに伴って信号の混信
および遅延が防止されるとともに、信頼性の高い良好な
配線構造が得られる等の効果がある。As explained above, according to the wiring structure of a semiconductor integrated circuit device according to the present invention, since a cavity is formed in an insulating film, a decrease in capacitance between conductor layers and relaxation of stress in the insulating film are reduced. As a result, signal interference and delay can be prevented, and a good wiring structure with high reliability can be obtained.
第１図（ａ）はこの発明の一実施例による半導体集積回
路装置の配線構造を示す断面図、第１図（ｂ）〜第１図
（８）はこの発明の他の実施例による半導体集積回路装
置の配線構造を示す断面図、第２図（ａ）。
第２図（ハ）および第３図は従来の半導体集積回路装置
の配線構造を示す断面図である。
■は基板、２は絶縁膜、３は配線膜、４は絶縁膜、５は
空洞、６は配線膜。
なお、図中、同一符号は同一、又は相当部分を示す。
代理人 大 岩 増 雄 （外２名）才 ｌ 図 ｅ
ａン
２７ 図（〆〕
才２図（４）
才２図（り
乙
手続補正書（自発）
昭和 ％２ 嘔 ３１Ｂ
１、事件の表示 特願昭 ６２−１２８１７ 号
２、発明の名称
半導体集積回路装置の配線構造
３、補正をする者
５、補正の対象
（１）明細書の発明の詳細な説明の欄
６、補正の内容
（１）明細書の第３頁第１行目に「ＶａｐｅｒＪとある
を、ｒＶａｐｏｒＪと補正する。
（２）同第４頁５行目に「膜圧減少に伴って、」とある
を、「膜厚減少に伴って、」と補正する。
（３）同第４頁第１０行目に「断線が生ずる等の」とあ
るを、「断線や欠損が生ずる等の」と補正する。
（４）同第４頁第１４行目〜１５行目に「断線が生じな
い」とあるを、「断線や欠損が生じない」と補正する。
（５）同第５頁第６行目〜７行目に［断線が防止されろ
ことになる。」とあるを、［断線や欠損が防止されるこ
とになる。」と補正する。
（６）同第５頁第１１行目〜１２行目に「絶縁性の向上
と」とあるを、「配線間容量の低減と」と補正する。
（７）同第５頁第１９行目に「絶縁性向上と」とあるを
、「配線間容量の低減と」と補正する。FIG. 1(a) is a sectional view showing the wiring structure of a semiconductor integrated circuit device according to one embodiment of the present invention, and FIG. 1(b) to FIG. 1(8) are semiconductor integrated circuit devices according to other embodiments of the present invention. FIG. 2(a) is a cross-sectional view showing the wiring structure of the circuit device. FIGS. 2(c) and 3 are cross-sectional views showing the wiring structure of a conventional semiconductor integrated circuit device. 2 is a substrate, 2 is an insulating film, 3 is a wiring film, 4 is an insulating film, 5 is a cavity, and 6 is a wiring film. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa (2 others) Figure e
Figure a 27 (end) Figure 2 Figure 4 (4) Figure 2 (Written Amendment to Procedures B (voluntary) Showa %2 31B 1. Indication of the case Patent Application No. 12817/1982 2. Name of the invention: Semiconductor integrated circuit Wiring structure of the device 3, person making the amendment 5, subject of the amendment (1) Detailed description of the invention column 6 of the specification, content of the amendment (1) “Vaper J and (2) In the 5th line of page 4 of the same document, the phrase "as the membrane pressure decreases," is corrected to "as the membrane thickness decreases." (3) In the same article In the 10th line of page 4, the phrase ``disconnection may occur, etc.'' is corrected to ``disconnection or damage may occur.'' (5) On page 5, lines 6 and 7 of the same page, the phrase ``breakage should be prevented.'' should be corrected. (6) On page 5, lines 11 and 12, the phrase ``improved insulation'' was replaced with ``reduction of inter-wiring capacitance.'' (7) In the 19th line of page 5, the phrase "improving insulation" is amended to read "reducing inter-wiring capacitance."
Claims (6)
気的に絶縁された半導体集積回路装置において、前記導
体間の絶縁膜部分に空洞が形成されていることを特徴と
する半導体集積回路装置の配線構造。(1) Wiring of a semiconductor integrated circuit device in which conductors are electrically insulated by being filled with an insulating film, characterized in that a cavity is formed in the insulating film portion between the conductors. structure.
ていることを特徴とする特許請求の範囲第１項記載の半
導体集積回路装置の配線構造。(2) The wiring structure for a semiconductor integrated circuit device according to claim 1, wherein the cavity is filled with gas having an arbitrary pressure.
絶縁膜によって囲まれていることを特徴とする特許請求
の範囲第１項記載の半導体集積回路装置の配線構造。(3) A wiring structure for a semiconductor integrated circuit device according to claim 1, wherein a cavity between adjacent conductors is surrounded by one or two types of insulating film.
よって囲まれていることを特徴とする特許請求の範囲第
１項記載の半導体集積回路装置の配線構造。(4) A wiring structure for a semiconductor integrated circuit device according to claim 1, wherein a cavity between adjacent conductors is surrounded by a conductor film and an insulating film.
いずれか又はこれらの積層構造からなることを特徴とす
る特許請求の範囲第１項記載の半導体集積回路装置の配
線構造。(5) The wiring structure of a semiconductor integrated circuit device according to claim 1, wherein the conductor is made of polycrystalline silicon, a metal, an impurity diffusion layer, or a laminated structure thereof.
、シリコンオキシナイトライド膜、金属酸化膜、有機絶
縁膜のいずれかからなることを特徴とする特許請求の範
囲第１項記載の半導体集積回路装置の配線構造。(6) The semiconductor integrated circuit according to claim 1, wherein the insulating film is made of any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a metal oxide film, and an organic insulating film. Equipment wiring structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1281787A JPS63179548A (en) | 1987-01-21 | 1987-01-21 | Wiring structure of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1281787A JPS63179548A (en) | 1987-01-21 | 1987-01-21 | Wiring structure of semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63179548A true JPS63179548A (en) | 1988-07-23 |
Family
ID=11815937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1281787A Pending JPS63179548A (en) | 1987-01-21 | 1987-01-21 | Wiring structure of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63179548A (en) |
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02218150A (en) * | 1988-12-16 | 1990-08-30 | Internatl Business Mach Corp <Ibm> | Method of providing electric insulating medium between aperin of superimposed members |
| US5001079A (en) * | 1988-06-29 | 1991-03-19 | Laarhoven Josephus M F G Van | Method of manufacturing a semiconductor device by forming insulating side walls with voids below overhangs |
| JPH03156929A (en) * | 1989-11-14 | 1991-07-04 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| US5444015A (en) * | 1992-12-15 | 1995-08-22 | International Business Machines Corporation | Larce scale IC personalization method employing air dielectric structure for extended conductors |
| US5486493A (en) * | 1994-02-25 | 1996-01-23 | Jeng; Shin-Puu | Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators |
| US5548159A (en) * | 1994-05-27 | 1996-08-20 | Texas Instruments Incorporated | Porous insulator for line-to-line capacitance reduction |
| US5661049A (en) * | 1994-02-14 | 1997-08-26 | United Microelectronics Corporation | Stress relaxation in dielectric before metallization |
| US5668398A (en) * | 1994-05-27 | 1997-09-16 | Texas Instruments Incorporated | Multilevel interconnect structure with air gaps formed between metal leads |
| US5751066A (en) * | 1994-05-27 | 1998-05-12 | Texas Instruments Incorporated | Structure with selective gap fill of submicron interconnects |
| US5759913A (en) * | 1996-06-05 | 1998-06-02 | Advanced Micro Devices, Inc. | Method of formation of an air gap within a semiconductor dielectric by solvent desorption |
| US5786624A (en) * | 1994-06-07 | 1998-07-28 | Texas Instruments Incorporated | Dual masking for selective gap fill of submicron interconnects |
| US5818111A (en) * | 1997-03-21 | 1998-10-06 | Texas Instruments Incorporated | Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials |
| US5837618A (en) * | 1995-06-07 | 1998-11-17 | Advanced Micro Devices, Inc. | Uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines |
| US5869379A (en) * | 1997-12-08 | 1999-02-09 | Advanced Micro Devices, Inc. | Method of forming air gap spacer for high performance MOSFETS' |
| US5953626A (en) * | 1996-06-05 | 1999-09-14 | Advanced Micro Devices, Inc. | Dissolvable dielectric method |
| US6054769A (en) * | 1997-01-17 | 2000-04-25 | Texas Instruments Incorporated | Low capacitance interconnect structures in integrated circuits having an adhesion and protective overlayer for low dielectric materials |
| US6160316A (en) * | 1998-03-04 | 2000-12-12 | Advanced Micro Devices, Inc. | Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths |
| US6208015B1 (en) | 1996-06-05 | 2001-03-27 | Advanced Micro Devices, Inc. | Interlevel dielectric with air gaps to lessen capacitive coupling |
| US6376330B1 (en) | 1996-06-05 | 2002-04-23 | Advanced Micro Devices, Inc. | Dielectric having an air gap formed between closely spaced interconnect lines |
| US6495917B1 (en) * | 2000-03-17 | 2002-12-17 | International Business Machines Corporation | Method and structure of column interconnect |
| US7557029B2 (en) | 2002-11-15 | 2009-07-07 | Sharp Kabushiki Kaisha | Semiconductor device and fabrication process thereof |
-
1987
- 1987-01-21 JP JP1281787A patent/JPS63179548A/en active Pending
Cited By (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5001079A (en) * | 1988-06-29 | 1991-03-19 | Laarhoven Josephus M F G Van | Method of manufacturing a semiconductor device by forming insulating side walls with voids below overhangs |
| JPH02218150A (en) * | 1988-12-16 | 1990-08-30 | Internatl Business Mach Corp <Ibm> | Method of providing electric insulating medium between aperin of superimposed members |
| JPH03156929A (en) * | 1989-11-14 | 1991-07-04 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| US5530290A (en) * | 1992-12-15 | 1996-06-25 | International Business Machines Corporation | Large scale IC personalization method employing air dielectric structure for extended conductor |
| US5444015A (en) * | 1992-12-15 | 1995-08-22 | International Business Machines Corporation | Larce scale IC personalization method employing air dielectric structure for extended conductors |
| US5661049A (en) * | 1994-02-14 | 1997-08-26 | United Microelectronics Corporation | Stress relaxation in dielectric before metallization |
| US5591677A (en) * | 1994-02-25 | 1997-01-07 | Texas Instruments Incorporated | Planarizeed multi-level interconnect scheme with embedded low-dielectric constant insulators |
| US5616959A (en) * | 1994-02-25 | 1997-04-01 | Texas Instruments Incorporated | Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators |
| US5486493A (en) * | 1994-02-25 | 1996-01-23 | Jeng; Shin-Puu | Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators |
| US5548159A (en) * | 1994-05-27 | 1996-08-20 | Texas Instruments Incorporated | Porous insulator for line-to-line capacitance reduction |
| US5668398A (en) * | 1994-05-27 | 1997-09-16 | Texas Instruments Incorporated | Multilevel interconnect structure with air gaps formed between metal leads |
| US5751066A (en) * | 1994-05-27 | 1998-05-12 | Texas Instruments Incorporated | Structure with selective gap fill of submicron interconnects |
| US5936295A (en) * | 1994-05-27 | 1999-08-10 | Texas Instruments Incorporated | Multilevel interconnect structure with air gaps formed between metal leads |
| US5786624A (en) * | 1994-06-07 | 1998-07-28 | Texas Instruments Incorporated | Dual masking for selective gap fill of submicron interconnects |
| US5837618A (en) * | 1995-06-07 | 1998-11-17 | Advanced Micro Devices, Inc. | Uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines |
| US5759913A (en) * | 1996-06-05 | 1998-06-02 | Advanced Micro Devices, Inc. | Method of formation of an air gap within a semiconductor dielectric by solvent desorption |
| US5953626A (en) * | 1996-06-05 | 1999-09-14 | Advanced Micro Devices, Inc. | Dissolvable dielectric method |
| US6091149A (en) * | 1996-06-05 | 2000-07-18 | Advanced Micro Devices, Inc. | Dissolvable dielectric method and structure |
| US6208015B1 (en) | 1996-06-05 | 2001-03-27 | Advanced Micro Devices, Inc. | Interlevel dielectric with air gaps to lessen capacitive coupling |
| US6376330B1 (en) | 1996-06-05 | 2002-04-23 | Advanced Micro Devices, Inc. | Dielectric having an air gap formed between closely spaced interconnect lines |
| US6054769A (en) * | 1997-01-17 | 2000-04-25 | Texas Instruments Incorporated | Low capacitance interconnect structures in integrated circuits having an adhesion and protective overlayer for low dielectric materials |
| US5818111A (en) * | 1997-03-21 | 1998-10-06 | Texas Instruments Incorporated | Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials |
| US5869379A (en) * | 1997-12-08 | 1999-02-09 | Advanced Micro Devices, Inc. | Method of forming air gap spacer for high performance MOSFETS' |
| US5959337A (en) * | 1997-12-08 | 1999-09-28 | Advanced Micro Devices, Inc. | Air gap spacer formation for high performance MOSFETs |
| US6160316A (en) * | 1998-03-04 | 2000-12-12 | Advanced Micro Devices, Inc. | Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths |
| US6495917B1 (en) * | 2000-03-17 | 2002-12-17 | International Business Machines Corporation | Method and structure of column interconnect |
| US7557029B2 (en) | 2002-11-15 | 2009-07-07 | Sharp Kabushiki Kaisha | Semiconductor device and fabrication process thereof |
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