JPS63173415A - Drive method for semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the tail current by constituting the titled device by a double gate GTO and a gate pulser and giving a difference to the start point time of two gate pulses in impressing a turn-off gate pulse especially so as to reduce the drop time without increase in the turn-off loss and power loss at forward voltage drop. CONSTITUTION:The device consists of a double gate GTO1, a reference gate pulse generating circuit 2, 2nd and 3rd pulses 3, 5 and an off-gate pulse delay circuit 4 and a reference pulse S1 and a low potential are isolated. The reference pulse S1 is repeated at an interval of t5-t1, a 1st gate pulse S2 gives an output from a time t1 to t2 and it is repeated. A turn-on signal S3 is synchronized with the said signal S1 and a turn-off signal S3 is retarded by the off-pulse of the gate S1 by t=t4-t3. The signal S5 is provided and a 2nd gate output is positive at a time t1 and an off-pulse at a time t4. The generation time of the signal S2 and the turn-off pulse of the S4 is made different by t to operate a double gate GTO1. Thus, the problem of long fall time of the anode current is solved by sucking a current by using two gates and the problem of the large initial value of the tail current is solved by using the 1st gate to suppress the injection of positive holes respectively.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention is a gate turn-off thyristor, and has gates on both the anode side N base (hereinafter referred to as anode base) and the cathode side P base (hereinafter referred to as cathode base). Gate turn-off thyristor with electrodes (hereinafter referred to as double gate GTO)
) on how to drive.

(Prior Art) Double gate GTO is currently under development and is not in use. Therefore, the problem is not clear, but since a drawback has become clear in the characteristics of single gate GTOs currently on the market, the problem will be described below as a problem of the prior art.

(Problem that the invention attempts to solve) FIG. 7 shows a single gate GTO and peripheral circuits.

In the figure, 101 is a single gate GTO 1102 is a turn-on gate power supply, 103 is a switch element, and 104 is a turn-on gate power supply.
is a turn-off gate power supply, 105 is a switch element, 10
6 is a main power supply, and 107 is a load.

FIG. 8 shows operating waveforms, and the operation will be explained using FIG. 5.

At time t1, the power supply 10 for turning on the switch element 103
2, the gate current 1. flows in the direction of the arrow shown, and the GTO 101 turns on.

The switch element 103 is opened before time t2, and the switch element 103 is opened before time t2.
When the switch element 105 is turned on, the off-state current M 105 causes a gate current of 1. flows in the direction opposite to the arrow shown. So-called current extraction is performed.

Then, the time until the current IA starts to decrease (=t3tz
) is called the accumulation time, and inside the GTO, the conduction region becomes narrower (hereinafter referred to as squeeze), and from time t8, the time decreases, and at the same time, the anode voltage vA increases. ■, decreases rapidly until time t4, at which time ("ta ta
) is called the descent time. The value of the anode current at time t4 is called the Tilmi flow initial value. At this point t4
From now on, ■, which flows until time t, is called the Tilmi flow,
This time (tx t, h) is called a tail period. This Tilmi current is a current generated because the residual charge in the N base shown in FIG. 7 is discharged.

Power loss p (=v^×■^) that occurs during the operation explained above
has the waveform shown in the bottom row of FIG.

In this waveform, the power loss that is large is the loss that occurs between time t3 and time t.

Breaking it down further, it is easy to see that the longer the descent time (=t4-t3), the greater the loss, and the greater the initial value of the Tilmi flow, the greater the gain and loss of tail travel.

Single-gate GTOs did not exhibit satisfactory characteristics with respect to the above two problems. Therefore, as a solution, GT
In order to shorten the lifetime of the carriers inside O, electron beam irradiation and metal doping were carried out, but if the process was carried out only to solve the above problems, the turn-on loss and forward voltage drop would of course increase rapidly, and it would not be possible to truly solve the problem. did not become. Hence the turn-on losses.

The problem to be solved is to shorten the drop time and reduce the Tilmi current value without increasing power loss due to forward voltage drop.

[Structure of the invention]

(Means for solving the problem) The means of the present invention consists of a double gate GTO and a gate pulser that drives it, and in particular, when applying a turn-off gate pulse, the double gate GTO is The gate application time difference is utilized by utilizing the operation peculiar to Gτ0.

(Function) The function of the present invention is to apply a positive bias to the first gate provided in the anode base layer to suck out electrons in the anode base layer and electrons injected from the cathode emitter, and to inject holes from the anode emitter. suppress. A negative bias is then applied to the second gate provided in the cathode base layer.

It suppresses the injection of electrons from the cathode and also functions to suck out holes from the cathode source layer.

(Example) Examples of the present invention will be specifically described below.

FIG. 1 is an example of the use of a double gate GTO using the present invention.

In the figure, 1 is a double gate GTO 12 which is a reference gate pulse generation circuit, 3 is a second gate pulser, 4 is an off-gate pulse delay circuit, and 5 is a second gate pulser.

In particular, since the first gate pulser 3 is used at a high potential, the signal S1
and low potential are insulated.

FIG. 2 is a time chart of signals 81 to S shown in FIG. 1 above.

The reference pulse S1 is a rectangular wave pulse that generates a signal at tl and becomes zero at tl, with an interval of 1. -1. is repeated.

The first gate pulse S2 is output from time t to time t2, and this is repeated.

In addition, the signal S for turn-on (shown positively) is synchronized with the signal S1, and the signal S for turn-off (shown negatively) is Δ1=14
-1. lags behind the off-pulse of the first gate S8. This signal 5sti-H is then output from the second gate at time t,
A positive pulse is generated at time t4, and an off pulse is generated at time t4.

As mentioned above, since the generation times of the turn-off pulses of the signals S2 and S differ by Δt, the double gate GT
The operations occurring inside O are shown in FIGS. 3(a) and 3(b).

FIG. 3 schematically shows the current flow distribution at turn-off, and the second gate in both (a) and (b) is omitted because it is open.

FIG. 5A shows a state in which a positive bias 6o is applied to the first gate 40b by a switch element or the like, and squeezing has begun to occur in the anode base layer. The electrons pass through the first gates 40a, 40
The hole injection region from the anode emitter P begins to shrink toward the center of the emitter. In the same figure (b), time has passed compared to the above (a), and the squeeze has progressed further. . In addition, injection of holes from the anode emitter is suppressed. however.

Electron injection into the cathode emitter N continues without being suppressed.

Next, as shown in the fourth [agony (a) and (b), the second gate 5
When a negative bias of 7o is applied to 0(a) and 0(b) using a switch not shown in the figure, and both the first and second gates are operated, the voltage is initially applied to the cathode side as shown in (a) of the same figure. Also, squeezing occurs, and injection of electrons from the cathode emitter N begins to be suppressed.

Furthermore, as time passes, the anode 20. The injection of holes and electrons from the cathode 30 is stopped, and the remaining charges are discharged from the two gates.

This state is near the point at which the Tilmi flow begins to flow.

As shown in Fig. 5, the waveforms of current and voltage actually flowing in the circuit are such that the current between the anode and cathode is 4 (solid line), and after the signal s2 of the first gate is applied (t,), the signal S of the second gate is
It is shown that when , is applied, the current rapidly approaches zero. At this time, vA is the inter-element voltage (also shown in FIG. 1), which is approximately 2000V.

As a comparative example, when the signal s2 of the first gate is made slower than the signal S of the second gate, the main current flowing between the elements becomes
As shown in FIG. 6, the voltage gradually decreases, which worsens the switching characteristics.

〔Effect of the invention〕

As is clear from comparing the operation described in the embodiment of the present invention with the problem of the prior art, the problem of the long fall time of the anode current can be solved by sucking out the current by two gates, thereby shortening the time.

Further, regarding the problem of a large initial value of the Tilmi flow, the first gate can suppress the injection of holes, so it can be significantly reduced.

The above effect ultimately results in a significant reduction in power loss. Furthermore, reducing power loss increases switching frequency, which has the effect of facilitating high-frequency driving.

[Brief explanation of the drawing]

Figure 1 is the basic circuit when using a double gate GTO, Figure 2 is a gate pulse time chart, Figure 3 is a current flow diagram when the double gate is turned off only by the first gate, and Figure 4 is is a current flow diagram when off-bias is applied to both the first and second gates, FIG. 5 is a waveform diagram showing circuit waveforms of an embodiment of the present invention, FIG. 6 is a waveform diagram of a comparative example, and FIG. FIG. 7 is a diagram of a single gate GTO and its peripheral circuitry, and FIG. 8 is a waveform diagram showing voltage, current waveforms, and power loss waveforms. 1... Double gate GT03... First gate pulser 5... Second gate pulser 20... Anode electrode 30... Cathode electrode 40... First gate electrode 50... Second gate electrode 60...First gate power supply 70...Second gate power supply 101...
・Single gate GTO106...Main power supply
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Claims (1)

[Claims] A PN junction is formed between an anode emitter layer having a first conductivity type and this anode emitter layer, and a PN junction is formed between an anode base layer having a second conductivity type and this anode base layer. and a semiconductor formed by forming a PN junction between a cathode base layer having a first conductivity type and a cathode emitter layer having a second conductivity type, or an anode emitter and an anode base. A four-layer semiconductor device comprising the above-mentioned semiconductor in which the electrodes are partially connected with low resistance, and the anode base layer has an electrode, which serves as a first gate, and the cathode base layer has an electrode, which serves as a second gate. and a gate pulse generator for driving the semiconductor device, the turn-off pulse applied to the semiconductor device is applied to the first and second gates at a point where the turn-off pulse is applied to the first and second gates. A method for driving a semiconductor device, characterized in that the semiconductor device is driven by making the gate of the semiconductor device faster.