JPS63164231U - - Google Patents

Info

Publication number
JPS63164231U
JPS63164231U JP5626487U JP5626487U JPS63164231U JP S63164231 U JPS63164231 U JP S63164231U JP 5626487 U JP5626487 U JP 5626487U JP 5626487 U JP5626487 U JP 5626487U JP S63164231 U JPS63164231 U JP S63164231U
Authority
JP
Japan
Prior art keywords
chip
push
pins
come
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5626487U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5626487U priority Critical patent/JPS63164231U/ja
Publication of JPS63164231U publication Critical patent/JPS63164231U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案に係るチツプ実装装置の一実施
例の直交する２方向からの一部破断側面図、第２
図は突上げピンの高さの変形例を示す平面図、第
３図および第４図は従来装置の一部破断側面図で
ある。 １１……コレツト、１３，１４，１５，１６…
…突上げピン、１７……半導体チツプ、１８……
エキスパンドテープ。 FIG. 1 is a partially cutaway side view of an embodiment of the chip mounting apparatus according to the present invention, as viewed from two orthogonal directions;
The figure is a plan view showing a modification of the height of the push-up pin, and FIGS. 3 and 4 are partially cutaway side views of the conventional device. 11...Collect, 13, 14, 15, 16...
...Pushing pin, 17...Semiconductor chip, 18...
Expand tape.

Claims (1)

【実用新案登録請求の範囲】 チツプの周辺部に当接する少なくとも３以上の
突上げピンを備え、エキスパンドテープ上に接着
された前記チツプを前記エキスパンドテープの下
面からコレツト方向に突き上げるチツプ実装装置
において、 前記少なくとも３以上の突上げピンのうち少な
くとも１つの突上げピンが、他の突上げピンより
も低い位置で前記チツプに当接するよう低くなつ
ていることを特徴とするチツプ実装装置。[Claims for Utility Model Registration] A chip mounting device comprising at least three push-up pins that come into contact with the periphery of a chip, and pushes up the chip bonded onto the expandable tape from the bottom surface of the expandable tape toward the collet, A chip mounting apparatus characterized in that at least one of the at least three or more push-up pins is lowered so as to come into contact with the chip at a lower position than the other push-up pins.
JP5626487U 1987-04-14 1987-04-14 Pending JPS63164231U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5626487U JPS63164231U (en) 1987-04-14 1987-04-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5626487U JPS63164231U (en) 1987-04-14 1987-04-14

Publications (1)

Publication Number Publication Date
JPS63164231U true JPS63164231U (en) 1988-10-26

Family

ID=30884925

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5626487U Pending JPS63164231U (en) 1987-04-14 1987-04-14

Country Status (1)

Country Link
JP (1) JPS63164231U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013077714A (en) * 2011-09-30 2013-04-25 Fujikura Ltd Semiconductor chip push-up piece, semiconductor chip push-up apparatus and semiconductor chip push-up method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5245873A (en) * 1975-10-08 1977-04-11 Hitachi Ltd Article adsorbing mechanism
JPS6144842B2 (en) * 1980-05-15 1986-10-04 Emu Deii Corp

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5245873A (en) * 1975-10-08 1977-04-11 Hitachi Ltd Article adsorbing mechanism
JPS6144842B2 (en) * 1980-05-15 1986-10-04 Emu Deii Corp

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013077714A (en) * 2011-09-30 2013-04-25 Fujikura Ltd Semiconductor chip push-up piece, semiconductor chip push-up apparatus and semiconductor chip push-up method

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