JPS63149879A - Alternate processing control system - Google Patents

Alternate processing control system

Info

Publication number
JPS63149879A
JPS63149879A JP29714786A JP29714786A JPS63149879A JP S63149879 A JPS63149879 A JP S63149879A JP 29714786 A JP29714786 A JP 29714786A JP 29714786 A JP29714786 A JP 29714786A JP S63149879 A JPS63149879 A JP S63149879A
Authority
JP
Japan
Prior art keywords
memory
data block
host
address
defective data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29714786A
Other languages
Japanese (ja)
Inventor
Shoichi Kano
Shinji Nishiyama
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP29714786A priority Critical patent/JPS63149879A/en
Publication of JPS63149879A publication Critical patent/JPS63149879A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To shorten a wiring/reading processing time and to prevent the deterioration in the processing efficiency of a system by executing a writing/reading processing to a memory in a device when there is a defective data block in a processing range.
CONSTITUTION: The contents of the ID of the defective data block are written according to the instructing address of a counter in the memory 11 based on the control of a control circuit 3 and an address at that time is transmitted to a memory 13. When a comparison circuit 10 detects that coincidence of the ID of the data block from a host device and the ID of the defective data block in the memory 11, in the case of a writing instruction, the data from the host device is written in the memory 13 according to the instruction address of the counter 12 and in the case of a reading instruction, the data from the memory 13 is fed to the host device. Accordingly, it is not required to write or read the defective data block in a disk device and the processing efficiency can be enhanced.
COPYRIGHT: (C)1988,JPO&Japio
JP29714786A 1986-12-12 1986-12-12 Alternate processing control system Pending JPS63149879A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29714786A JPS63149879A (en) 1986-12-12 1986-12-12 Alternate processing control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29714786A JPS63149879A (en) 1986-12-12 1986-12-12 Alternate processing control system

Publications (1)

Publication Number Publication Date
JPS63149879A true JPS63149879A (en) 1988-06-22

Family

ID=17842808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29714786A Pending JPS63149879A (en) 1986-12-12 1986-12-12 Alternate processing control system

Country Status (1)

Country Link
JP (1) JPS63149879A (en)

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