JPS63142876A - Hall element device - Google Patents

Hall element device

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Publication number
JPS63142876A
JPS63142876A JP61290852A JP29085286A JPS63142876A JP S63142876 A JPS63142876 A JP S63142876A JP 61290852 A JP61290852 A JP 61290852A JP 29085286 A JP29085286 A JP 29085286A JP S63142876 A JPS63142876 A JP S63142876A
Authority
JP
Japan
Prior art keywords
hall
input
hall element
magnetic field
currents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61290852A
Other languages
Japanese (ja)
Inventor
Saikichi Sekido
関戸 才吉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61290852A priority Critical patent/JPS63142876A/en
Publication of JPS63142876A publication Critical patent/JPS63142876A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To isolate the input and the output excellently, and to form a Hall element device in a monolithic manner by including a semiconductor Hall element detecting a magnetic field in the fixed direction and a wiring path causing currents to spirally flow through the periphery of the semiconductor Hall element and shaping a magnetic field in the direction of detection of the magnetic field. CONSTITUTION:When a voltage is applied between power input terminals VSS and VDD and a potential higher than a threshold level is applied at a gate input terminal VG, an n channel is formed between a source 3 and a drain 4, and currents flow. When currents are caused to flow through an input-signal wiring path 2 through input terminals VIA, VIB at that time, a magnetic field is generated in the direction vertical to a MOS type Hall element 1, currents between the source 3 and the drain 4 are subject to a Hall effect, and Hall voltage is generated between Hall-effect output terminals HA, HB. When a control pulse signal psiP is turned ON and currents are caused to flow through the MOS type Hall element 1, the Hall voltage proportional to currents flowing between the input terminal pair VIA, VIB is generated between HA and HB. The voltage is input to an amplifier 8 when a control pulse signal psiS is turned ON. The amplified signal is latched, and held as an output signal VO.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はホール素子装置に関し、特に入力信号を電流と
して与え入力の電位とは直接に影響のない電圧によって
出力信号を得るインタフェースとしての信号変換装置に
関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a Hall element device, and in particular to signal conversion as an interface in which an input signal is given as a current and an output signal is obtained by a voltage that has no direct influence on the input potential. Regarding equipment.

〔従来の技術〕[Conventional technology]

従来、この種の信号変換手段としては、メカニカルリレ
ー、フォトカプラー等を使用していた。
Conventionally, mechanical relays, photocouplers, etc. have been used as this type of signal conversion means.

メカニカルリレーは、入力信号である電流をコイルに流
し、その電磁力により鉄片等を引付ける作用によって出
力側の回路を断成し、出力を得てお夛、またフォトカプ
ラーは、入力電流をLEDに流して発光させ、その元を
フォトダイオードなどの受光素子によって光電変換して
出力を得ている。
Mechanical relays pass a current, which is an input signal, through a coil, and the electromagnetic force attracts a piece of iron, etc., to disconnect the output side circuit and obtain an output.Photocouplers pass the input current to an LED. The source of the light is converted into electricity by a light-receiving element such as a photodiode to obtain an output.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述したメカニカルリレーは機械的動作を含むため動作
速度が遅く、耐久性の向上、小型化が困難という欠点が
あり、また、フォトカプラーはモノリシック化が困難で
あり、半導体の素材として信頼度の高いシリコンが使用
できないという欠点がある。
The above-mentioned mechanical relays have the drawbacks of slow operation speed because they involve mechanical operation, and difficulty in improving durability and miniaturization.In addition, photocouplers are difficult to make monolithic and are highly reliable as semiconductor materials. The disadvantage is that silicon cannot be used.

本発明の目的は、このよりな欠点を除き、入力側と出力
側とが良好にアイソレーションされ、モノリシックに形
成できるホール素子装置全提供することにある。
An object of the present invention is to eliminate this further drawback and provide a complete Hall element device whose input side and output side are well isolated and which can be formed monolithically.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のホール素子装置は、電流供給源の端子対とホー
ル効果出力端子対とを有し所定方向の磁界を検出する半
導体ホール素子と、この半導体ホール素子の周囲に電流
を渦状に流して前記磁界検出方向の磁界を形成する配線
路とを含み構成てれる。
The Hall element device of the present invention includes a semiconductor Hall element that has a pair of terminals for a current supply source and a pair of Hall effect output terminals and detects a magnetic field in a predetermined direction; and a wiring path that forms a magnetic field in the magnetic field detection direction.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の斜視図、第2図は第1図の
MO8型ホール累子1を一部断面図で示した斜視図であ
る。MO8型ホール素子10目シに入力信号配線路2を
設け、この人力信号配線路2の両端を入力端子付■工A
、VXBに接続する。
FIG. 1 is a perspective view of an embodiment of the present invention, and FIG. 2 is a partially sectional perspective view of the MO8 type Hall resistor 1 shown in FIG. An input signal wiring path 2 is provided at the 10th hole of the MO8 type Hall element, and both ends of this manual signal wiring path 2 are connected to input terminals.
, connect to VXB.

M(JS型ホール累+1はP型基板の上に形成され、そ
の四辺にn型拡散層を設け、その対向位置をソース3.
ドレイン4としてそれぞれ電源入力端子y8.VDDV
c接αし、もう一方の対向位置の拡散層5,6はそれぞ
れホール効果出力端子HA、HBと接続し、ゲート電極
はゲート入力端子■。と接続する。
M (JS type hole stack +1 is formed on a P type substrate, n type diffusion layers are provided on its four sides, and the opposing position is placed on the source 3.
As drains 4, power input terminals y8. VDDV
The diffusion layers 5 and 6 at the other opposing positions are connected to the Hall effect output terminals HA and HB, respectively, and the gate electrode is the gate input terminal ■. Connect with.

電源入力端子VSsVDD間に電圧を与え、ゲート入力
端子■。にスレッショールドレベル以上の電位を与える
と、ソース3.ドレイン4間にnチャンネルが形成され
、電流が流れる。このとき入力端子■XA、vXBを通
して、入力信号配線路2に電流を流すと、MO8型ホー
ル累子1を対して垂直な方向に磁場が発生し、ソース3
とドレイン4間の電流に対してホール効果を及はし、ホ
ール効果出力端子HA、HB間にホール電圧を発生させ
る。
Apply voltage between power supply input terminals VSsVDD and gate input terminal ■. When a potential above the threshold level is applied to source 3. An n-channel is formed between the drains 4 and current flows. At this time, when a current is applied to the input signal wiring path 2 through the input terminals
The Hall effect is exerted on the current between the output terminals HA and the drain 4, and a Hall voltage is generated between the Hall effect output terminals HA and HB.

第3図は第1図の実施例を含むインタフェース回路のブ
ロック図である。MO8型ホール累子累子ゲート入力端
子V。K制御回路10からの制御パルス信号φアを供給
し、ホール効果出力端子HA。
FIG. 3 is a block diagram of an interface circuit including the embodiment of FIG. MO8 type Hall gate gate input terminal V. A control pulse signal φA from the K control circuit 10 is supplied to the Hall effect output terminal HA.

HBをトランスファーゲート7の入力端子と接続する。Connect HB to the input terminal of transfer gate 7.

このトランスファゲート7のゲート端子は制御回路10
の制御パルス信号φ3が与えられ、その出力端子は増幅
器8の入力端子と泉伏される。
The gate terminal of this transfer gate 7 is connected to the control circuit 10.
A control pulse signal φ3 is applied, and its output terminal is connected to the input terminal of the amplifier 8.

この増幅器8のクロック入力端子には制御回路100制
御パルス信号φ、が与えられ、その出力端子はラッチ回
路9の入力端子と接αされる。ラッチ回路9のクロック
入力端子は制御回路10の制御パルス信号φ。が与えら
れ、ラッチ回路9の出力をこのインタフェース回路の出
力端子■。となる。
A control pulse signal φ of a control circuit 100 is applied to a clock input terminal of this amplifier 8, and its output terminal is connected to an input terminal of a latch circuit 9. The clock input terminal of the latch circuit 9 receives the control pulse signal φ of the control circuit 10. is given, and the output of the latch circuit 9 is the output terminal of this interface circuit. becomes.

制御パルス信号φPをONとしてMO8型ホール累子1
を電流を流すと、入力端子対VA、VxB! 間に流れるX流に比例したホール電圧が)IA 、 H
8間に発生する。この電圧は制御パルス信号φ、がON
のときに増幅器81C人力され、信号φ5がOFFとな
るとその電圧がホールドされる。また、このとき信号り
を(JFFとするとMO8型ホール素子IKi流が流れ
ず、消費電流の浪費を防ぐ。増幅器8には人力インピー
ダンスの高いM08型増幅器を用い、制御パルス φえ
をクロック入力とするダイナミック増幅器として消費電
流を低減できる。増幅器れた信号はラッチ回路9に人力
され、制御パルス φ。によってラッチされ出力信号V
When the control pulse signal φP is turned ON, MO8 type Hall transducer 1
When a current flows through the input terminals VA, VxB! The Hall voltage proportional to the X current flowing between )IA, H
Occurs between 8 and 8. This voltage is the control pulse signal φ, which is ON.
When the amplifier 81C is turned off, the voltage is held when the signal φ5 is turned off. At this time, if the signal is set to (JFF), the MO8 type Hall element IKi current will not flow, preventing wasted current consumption.The amplifier 8 is an M08 type amplifier with high human power impedance, and the control pulse φ is used as the clock input. As a dynamic amplifier, the current consumption can be reduced.The signal output from the amplifier is input to the latch circuit 9, and is latched by the control pulse φ.
.

としてホールドされる。以上のように微弱なホール電圧
を増幅して出力することがモノリシックなICとして実
現可能となる。
will be held as . As described above, it becomes possible to amplify and output a weak Hall voltage as a monolithic IC.

である。ホール素子1のソース3を接地し、ドレイン4
を電源端子■DDと接続し、入力信号の配線路に二1m
の配線層21.22を用いる。入力電流は入力端子■X
Aから第1層の配線路21を通ってMO8型ホール累子
累子回りを複数1gIまわり、コンタクト23から第2
層の配線路22に、$p、同一方向に複数回まわって入
力端子■工、へと流れる。
It is. The source 3 of the Hall element 1 is grounded, and the drain 4
Connect it to the power terminal ■DD, and connect it to the input signal wiring path for 21 m.
wiring layers 21 and 22 are used. Input current is input terminal
From A, pass through the wiring path 21 of the first layer, go around the MO8 type hole cursor for a plurality of 1gI, and from the contact 23 to the second layer.
In the wiring path 22 of the layer, the signal $p turns several times in the same direction and flows to the input terminal 2.

このように配線路を複数回まわすことによって同一の電
流に対して強い磁界を発生式せることかできる。この配
線層をさらに増加烙せればさらに大きな出力が得られる
By turning the wiring path multiple times in this way, it is possible to generate a strong magnetic field for the same current. If the number of wiring layers is further increased, even greater output can be obtained.

第5図は本発明の第3の実施例のレイアクト図である。FIG. 5 is a layout diagram of a third embodiment of the present invention.

ここでは第4図の実施例を二個直列に接続したもので、
一方の入力信号配線路を他方と逆回しにしている。すな
わち、入力電流は入力端子VXAから第1層の配線路3
1を右回りに進み、コンタクト32から第2層の配線路
33に入って右回りに進み、今度は次のM08ホール素
子の回りを左回りに進み、コンタクト34から第1層の
ヘと流れる。
Here, two of the embodiments shown in Fig. 4 are connected in series.
One input signal wiring path is reversed from the other. In other words, the input current flows from the input terminal VXA to the wiring path 3 of the first layer.
1 in a clockwise direction, enters the wiring path 33 of the second layer from the contact 32, continues clockwise, then counterclockwise around the next M08 Hall element, and flows from the contact 34 to the first layer. .

このようにすると、2つのMO8ホールS子に対して発
生する磁界の向きは逆方向となる。また、ソース36.
41を接地し、ドレイン37 、40を電源端子vDD
と接続して電流が左右逆方向に流れるようにすると、ホ
ール効果によって発生する端子38.39の間、端子4
2.43の間のホール電圧は上下同一方向となり、端子
39.42を接続すると、端子38と接続したHAと端
子43との間にはそれぞれのホール電圧を加算した電圧
が得られる。
If this is done, the directions of the magnetic fields generated for the two MO8 hole S atoms will be in opposite directions. Also, source 36.
41 is grounded, and the drains 37 and 40 are connected to the power supply terminal vDD.
When connected to the terminals 38 and 39 so that the current flows in opposite directions to the left and right, the terminal 4
The Hall voltages between 2.43 and 2.43 are in the same direction in the upper and lower directions, and when terminals 39 and 42 are connected, a voltage obtained by adding the respective Hall voltages is obtained between HA connected to terminal 38 and terminal 43.

このようにすると入力端子配線路fMO8ホール素子の
近くに多くとることができ、相対的に配線路の半径を小
器くして効率よく磁界を発生させることができる。また
、逆向きの磁界を使用するということは外部からの電出
波ノイズの影響を互いに補償しあうという利点がある。
In this way, a large number of input terminal wiring paths fMO8 can be provided near the Hall element, and the radius of the wiring path can be made relatively small to efficiently generate a magnetic field. Furthermore, using magnetic fields in opposite directions has the advantage that they mutually compensate for the effects of external electromagnetic wave noise.

ここでは二つのブロックを直列に接続しているが、多く
のブロックを接続すればその効果も増加する。またブロ
ックを90@回転させ、を流の向きを直父させたものを
接続すれば、結晶方向の差によるキャリア移動度の差を
補償する効果もある。
Here, two blocks are connected in series, but the effect will increase if more blocks are connected. Furthermore, if the block is rotated by 90° and connected with the flow direction directly aligned, there is an effect of compensating for the difference in carrier mobility due to the difference in crystal orientation.

ここで、入力端子によってつくられる磁場およびその磁
場によって発生するホール電圧について検討する。
Here, we will consider the magnetic field created by the input terminal and the Hall voltage generated by the magnetic field.

よく仰られているように半径几(m)の円電流i (A
 )がn回まわっていると、その中心部につくられる磁
場Bは次式により、E?見られる。
As is often said, the circular current i (A
) rotates n times, the magnetic field B created at its center is E? Can be seen.

但し、μ。=4π×lO〔ヘンリー/m〕。However, μ. =4π×lO [Henry/m].

1〔クエーバ工/m2)=10 ’ Cガウス〕。1 [quaver work/m2) = 10’ C Gauss].

本実施例に示したM08型ホール累1が一辺100μm
の正方形であって入力信号配#S路2がその近くにある
とすると、2a=xoo(μm〕となり、これらを(1
)式に代入すると次のようになる。
The M08 type hole stack 1 shown in this example is 100 μm on a side.
If it is a square and the input signal path #S path 2 is near it, then 2a=xoo (μm), and these are (1
) Substituting into the formula yields the following:

−万、「電気学会雑誌」102巻5号384頁の論文「
集積化磁気センサ」によると、ホール電圧vHは次式で
表される。
-Man, paper in ``Journal of the Institute of Electrical Engineers of Japan,'' Vol. 102, No. 5, p. 384, ``
According to the integrated magnetic sensor, the Hall voltage vH is expressed by the following equation.

■H=−α(W/L)μnvDDB  ・・・・・・・
・−(3)但し、α:を極の短絡効果による形状効果係
数W:チャンネル巾 L:チャンネル長 ここでa=s OOガクス、■DD=5Vに対してホー
ル電圧V、工=15mVが得られる。例えば、第5図に
おいて谷配線層の巻線数を10とすると二層でn=20
.11流をt = 0.2 s Aとして(2)式に代
入すると、2つのホール素子に発生するホール電圧はそ
れぞれ15mVであって合計30mVとなり、さらに増
幅器を設けるとインタフェース回路が実現可能である。
■H=-α(W/L)μnvDDB ・・・・・・・・・
・-(3) However, α: Shape effect coefficient due to short-circuit effect of poles W: Channel width L: Channel length where a=s OO Gax, It will be done. For example, in Figure 5, if the number of turns in the valley wiring layer is 10, then n = 20 in two layers.
.. By substituting the 11 current into equation (2) with t = 0.2 s A, the Hall voltage generated in the two Hall elements is 15 mV each, giving a total of 30 mV.If an amplifier is further provided, an interface circuit can be realized. .

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、人力信号である電流に
よって磁界を発生させ、その磁界によるホール効果の発
生電圧を出力信号とすることにより、入力側と出力側と
を別電源で動作させ、極めて艮好な入出力のアイソレー
ジ目ンを有するモノリシックな牛導体装[を得ることが
できる。また、ホール素子及びその周辺回路としてバイ
ポーラ型の回路によっても実現できることは言うまでも
ない0
As explained above, the present invention generates a magnetic field using a current, which is a human input signal, and uses the voltage generated by the Hall effect due to the magnetic field as an output signal, thereby operating the input side and the output side with separate power supplies. It is possible to obtain a monolithic conductor package with very good input and output isolation. It goes without saying that the Hall element and its peripheral circuit can also be realized using a bipolar type circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例の斜視図、第2図は第1
図のM OS型ホール素子1を部分断面で示しt斜視図
、第3図は第1図の実施例をきむインタフェース回路の
ブロック図、第4図は本発明の第2の実施例のレイアウ
ト図、第5図は本発明の第3の実施例のレイアクト図で
ある。 1・・・・・・M08型ホール素子、2・・・・・・入
力信号配+tM路、3,36.41・・・・・・ソース
、4 、37.40・・・・・・ドレイン、5,6,3
8,39,42,43・・・・・・拡散+dの端子、7
・・・・・・トランスファゲート、8・・・・・・増幅
器、9・・・・・・ラッチ回路、10・・・・・・制御
回路%21,31,35・・・・・・第1層の配線路、
22.33・・・・・・第2層の配線路、23,32゜
34・・・・・・コンタクト、VXA、Vより・・・・
・・入力端子対、HA、HB・・・・・・ホール効果出
力端子対、vo・・・・・・ゲート入力端子、vDDV
s8・・・・・・ミノ入力端子対。 半l ワ 磐2 図 第3 凹 臀4 ロ ’Ja HA HB 信S 図
FIG. 1 is a perspective view of the first embodiment of the present invention, and FIG. 2 is a perspective view of the first embodiment of the present invention.
FIG. 3 is a block diagram of an interface circuit that implements the embodiment of FIG. 1, and FIG. 4 is a layout diagram of a second embodiment of the present invention. , FIG. 5 is a layout diagram of a third embodiment of the present invention. 1... M08 type Hall element, 2... Input signal wiring + tM path, 3, 36.41... Source, 4, 37.40... Drain ,5,6,3
8, 39, 42, 43... Diffusion +d terminal, 7
...Transfer gate, 8...Amplifier, 9...Latch circuit, 10...Control circuit %21, 31, 35...No. 1 layer wiring path,
22.33...2nd layer wiring route, 23,32°34...Contact, from VXA, V...
...Input terminal pair, HA, HB...Hall effect output terminal pair, vo...Gate input terminal, vDDV
s8...Mino input terminal pair. Half l Wa Iwa 2 Figure 3 Concave buttocks 4 Ro'Ja HA HB Shin S Figure

Claims (1)

【特許請求の範囲】[Claims] 電流供給源の端子対とホール効果出力端子対とを有し所
定方向の磁界を検出する半導体ホール素子と、このホー
ル素子の周囲に電流を渦状に流し前記磁界検出方向に磁
界を形成する配線路とを含むことを特徴とするホール素
子装置。
A semiconductor Hall element that has a current supply source terminal pair and a Hall effect output terminal pair and detects a magnetic field in a predetermined direction, and a wiring path that flows a current in a spiral around the Hall element and forms a magnetic field in the magnetic field detection direction. A Hall element device comprising:
JP61290852A 1986-12-05 1986-12-05 Hall element device Pending JPS63142876A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61290852A JPS63142876A (en) 1986-12-05 1986-12-05 Hall element device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61290852A JPS63142876A (en) 1986-12-05 1986-12-05 Hall element device

Publications (1)

Publication Number Publication Date
JPS63142876A true JPS63142876A (en) 1988-06-15

Family

ID=17761320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61290852A Pending JPS63142876A (en) 1986-12-05 1986-12-05 Hall element device

Country Status (1)

Country Link
JP (1) JPS63142876A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008016103A1 (en) * 2006-08-03 2008-02-07 Hiroshima University Current amplifying device and current amplifying method
JP2013504885A (en) * 2009-09-17 2013-02-07 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Integrated circuits for information transmission
JP2016025158A (en) * 2014-07-17 2016-02-08 学校法人 龍谷大学 Magnetic field sensor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008016103A1 (en) * 2006-08-03 2008-02-07 Hiroshima University Current amplifying device and current amplifying method
US7902919B2 (en) 2006-08-03 2011-03-08 Hiroshima University Current amplifying element and current amplification method
JP5283119B2 (en) * 2006-08-03 2013-09-04 国立大学法人広島大学 Current amplifying element and current amplifying method
JP2013504885A (en) * 2009-09-17 2013-02-07 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Integrated circuits for information transmission
JP2016025158A (en) * 2014-07-17 2016-02-08 学校法人 龍谷大学 Magnetic field sensor

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