JPS63136133A - Information processing circuit - Google Patents

Abstract

PURPOSE:To increase the number of words of the data to be held without increasing the word length of a microinstruction by writing the data on a data bus into a register equivalent to a single word and at the same time transferring the data stored in each register to other different registers respectively. CONSTITUTION:When a write command is delivered, the b-bit data on a data bus Bb is written into a b-bit register RbO via a selector SbO. In this case, the data on registers RbO-Rbm-2 are written into registers Rb1-Rbm-1 respectively and the data stored in the Rbm-1 is lost. When a read instruction is received, the b-bit data of the RbO is read into the bus Bb via a bus driver Db. At the same time, the data of Rb1-Rbm-1 are written into RbO-Rbm-2 together with the data of the RbO written into the Rbm-1. Thereafter the data of RbO-Rbm-1 are never lost.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an information processing circuit, and particularly to an information processing circuit that is connected to a data bus inside a microcontroller and temporarily retains data on the data bus. be used in general-purpose registers.

(Prior Art) Conventionally, as shown in FIG. 3, an information processing circuit of this type has b registers RO to Rb-1 and b buses, where b is the number of bits of a data bus. Driver DO~Db
-1, and data bus BO-Bb-
It had the function of writing data on the data bus BO-Bb by 1 word F, and the function of reading the written data onto the data bus BO-Bb.

Furthermore, as shown in the circuit diagram of FIG. 4, the b-bit general-purpose registers RbO to Rbn-1 shown in the circuit diagram of FIG.
There is a configuration that can hold data for n words by connecting to n data buses.

(Problem to be Solved by the Invention) However, the general-purpose registers of the conventional microprocessor described above have only as many registers as the number of bits of the data bus, so they can only hold one word of data. There is a problem.

In addition, the configuration shown in FIG. 4 using n general-purpose registers shown in the circuit diagram of FIG. 3 can hold data for n words, but the type of microinstruction There is a problem in that it is necessary to prepare n times more than in the case of . That is, the word length of the microinstruction must be increased. Furthermore, since the number of bus drivers is required to be one times that of the configuration shown in FIG. 3, there is a problem that the scale of the circuit increases.

(Means and operations for solving the problem) The information processing circuit according to the present invention includes a register that receives and holds data on a data bus, and a register that receives and sends the data held in this register to the data bus. The register includes a state bus driver and a selector that selects data to be held in the register, and the register has a storage capacity that can hold multiple words of data at the same time. one of them
The data on the data bus is written to a word worth of registers, and at the same time, the data held in each register except one register is transferred to each different register other than the register to which the data on the data bus is written. , a read command transfers the data held in all registers to different registers, and at the same time, in the case of the write command, the data held in the register to which data on the data bus is written is transferred to the bus. It is characterized by being sent to the data bus via the driver.

Therefore, in contrast to the general-purpose registers of the conventional microprocessor described above, the present invention can hold multiple words of data without increasing the word length of microinstructions or increasing the number of bus drivers. It has an original content.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The data bus Bb is a data bus inside the microprocessor and has b bits. b-bit registers RbO to Rbm
-1 are b-bit registers that manually hold b-bit data from the selectors sboS-sbm-1. The output data of Rb1-Rbm-2 is Sb2, respectively.
- Input to Sbm-1 and SbOSbo-5b. Rb
The output data of O is input to a tri-state bus driver Db of sbi, Sbm-1 and b bits. Rbm-
The output data of 1 is manually input to Sbm-2. The output of bus driver Db is connected to data bus Bb.

Next, the operation will be explained.

When a write command is issued to this general-purpose register by a microinstruction inside the microprocessor, the data bus Bb
The b-bit data of is written to the b-bit register RbO via the selector SbO. At this time, at the same time,
The data for Rb0-Rbm-2 are Rbl-Rbm-, respectively.
Written to 1. The data in Rbm-1 will be lost. When a read command is issued to this general-purpose register by a microinstruction inside the microprocessor, b-bit data in RbO is read out to data bus Bb via bus driver Db. At the same time, Rb1-Rb
The data of m-1 is written to RbO to Rbm-2, and R
The data in bO should be written to Rbm-1. Therefore, at this time, none of the data from RbO to Rbm-1 is lost.

When a microinstruction inside the microprocessor issues one read command to this general-purpose register after one write command, the data on the data bus Bb is written to the register RbO, and the data is transferred via the bus driver Db. The data is read out onto bus Bb. This is similar to the operation of the prior art general purpose register of FIG.

When a single write command is issued to this general-purpose register by a microinstruction inside the microprocessor, m≧
If it is 1, data is written to registers Rb0-Rb1-1. The data written in RbO to Rb1-1 can be read by k times of read instructions.

However, k≧1, and the number of k changes depending on the order in which data is read.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

The b-bit selector sb selects the b-bit data on the data bus Bb and the b-bit data on the register Rb2,
Output to RbO. The output of RbO is input to Rbl, and the output of Rbl is input to Rb2. b-bit bus driver Db
is a bus driver that receives data on Rbo and outputs it to data bus Bb.

When a write command by a microinstruction is issued to this general-purpose register, the data on data bus Bb is written to RbO, the data on RbO is written to Rbl, and the data on Rbl is written to R.
Transferred to b2. When a read command by a microinstruction is issued to this general-purpose register, the data in RbO becomes Db.
The data is read out to data bus Bb via , and transferred to Rbl.

At the same time, data in RbO is transferred to Rbl, and data in Rb1 is transferred to Rb2.

This second embodiment has the advantage that the number of selectors is small and the hardware scale is small.

(Effects of the Invention) As explained above, the general-purpose register of the microprocessor of the present invention can hold data without increasing the types of microinstructions inside the microprocessor, that is, without increasing the word length of the microinstructions. This has the effect of increasing the number of words. Furthermore, since the number of data words to be held can be increased without increasing the number of bus drivers, there is an effect that the hardware scale can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention;
The figure is a circuit diagram showing the configuration of the second embodiment of the present invention, Figure 3 is a circuit diagram of a conventional example, and Figure 4 shows a configuration in which the general-purpose register of the conventional example shown in Figure 3 is connected to n data buses. FIG. RbO~Rbm-1/φ/b bit register, SbO
Sbo-5b... b bit selector, Db...
...b-bit bus driver, Bb...contention, b-bit, soto data bus.

Claims (1)

[Claims] In an information processing circuit that has a register that receives and holds data on a data bus through a selector, and a tristate bus driver that receives the data held in this register and sends it to the data bus, the register can simultaneously store multiple words. It has a storage capacity capable of holding data, and in response to a write command, the data on the data bus is written to one word of the registers through the selector, and at the same time, one register is removed. The data held in each register is transferred to different registers other than the register to which the data on the data bus is written, and by a read command, the data held in all registers is transferred to different registers. and at the same time, data held in a register to which data on the data bus is written in the case of the write command is sent out to the data bus via the bus driver.